subject:"\[\[ARM\/AArch64\]\[testsuite\] 05\/36\] Add vldX

Re: [[ARM/AArch64][testsuite] 05/36] Add vldX_dup test.

2015-01-22 Thread Tejas Belagod







LGTM.


Thanks, I should mention that this test fails on aarch64_be, because
of pending Alan's patches.


A few big-endian fixes were checked in last night. Do you mean this?

r219957 | rsandifo | 2015-01-21 17:53:04 + (Wed, 21 Jan 2015) | 6 lines

gcc/
2015-01-25  Alan Hayward  alan.hayw...@arm.com

* rtlanal.c (subreg_get_info): Exit early for simple and common
cases.


Thanks,
Tejas.

Re: [[ARM/AArch64][testsuite] 05/36] Add vldX_dup test.

2015-01-22 Thread Christophe Lyon

On 22 January 2015 at 17:17, Tejas Belagod tejas.bela...@arm.com wrote:



 LGTM.

 Thanks, I should mention that this test fails on aarch64_be, because
 of pending Alan's patches.


 A few big-endian fixes were checked in last night. Do you mean this?

 r219957 | rsandifo | 2015-01-21 17:53:04 + (Wed, 21 Jan 2015) | 6 lines

 gcc/
 2015-01-25  Alan Hayward  alan.hayw...@arm.com

 * rtlanal.c (subreg_get_info): Exit early for simple and common
 cases.


Yes. I committed my test as r219914 and saw my automatic validation
results as FAIL for aarch64_be.
I expect them to move to PASS when r219957 will be validated. If not,
I'll let you know :-)


 Thanks,
 Tejas.

Re: [[ARM/AArch64][testsuite] 05/36] Add vldX_dup test.

2015-01-19 Thread Marcus Shawcroft

On 16 January 2015 at 18:12, Christophe Lyon christophe.l...@linaro.org wrote:
 On 16 January 2015 at 16:20, Tejas Belagod tejas.bela...@arm.com wrote:
 On 13/01/15 15:18, Christophe Lyon wrote:


  * gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c: New file.


 Thanks, I should mention that this test fails on aarch64_be, because
 of pending Alan's patches.



OK, thanks /Marcus

Re: [[ARM/AArch64][testsuite] 05/36] Add vldX_dup test.

2015-01-16 Thread Tejas Belagod


On 13/01/15 15:18, Christophe Lyon wrote:


 * gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c: New file.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c 
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c
new file mode 100644
index 000..53cd8f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c
@@ -0,0 +1,671 @@
+#include arm_neon.h
+#include arm-neon-ref.h
+#include compute-ref-data.h
+
+/* Expected results.  */
+
+/* vld2_dup/chunk 0.  */
+VECT_VAR_DECL(expected_vld2_0,int,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
+  0xf0, 0xf1, 0xf0, 0xf1 };
+VECT_VAR_DECL(expected_vld2_0,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff0, 0xfff1 
};
+VECT_VAR_DECL(expected_vld2_0,int,32,2) [] = { 0xfff0, 0xfff1 };
+VECT_VAR_DECL(expected_vld2_0,int,64,1) [] = { 0xfff0 };
+VECT_VAR_DECL(expected_vld2_0,uint,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
+   0xf0, 0xf1, 0xf0, 0xf1 };
+VECT_VAR_DECL(expected_vld2_0,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff0, 0xfff1 
};
+VECT_VAR_DECL(expected_vld2_0,uint,32,2) [] = { 0xfff0, 0xfff1 };
+VECT_VAR_DECL(expected_vld2_0,uint,64,1) [] = { 0xfff0 };
+VECT_VAR_DECL(expected_vld2_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
+   0xf0, 0xf1, 0xf0, 0xf1 };
+VECT_VAR_DECL(expected_vld2_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff0, 0xfff1 
};
+VECT_VAR_DECL(expected_vld2_0,hfloat,32,2) [] = { 0xc180, 0xc170 };
+VECT_VAR_DECL(expected_vld2_0,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+   0x33, 0x33, 0x33, 0x33,
+   0x33, 0x33, 0x33, 0x33,
+   0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld2_0,int,16,8) [] = { 0x, 0x, 0x, 0x,
+   0x, 0x, 0x, 0x };
+VECT_VAR_DECL(expected_vld2_0,int,32,4) [] = { 0x, 0x,
+   0x, 0x };
+VECT_VAR_DECL(expected_vld2_0,int,64,2) [] = { 0x,
+   0x };
+VECT_VAR_DECL(expected_vld2_0,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+0x33, 0x33, 0x33, 0x33,
+0x33, 0x33, 0x33, 0x33,
+0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld2_0,uint,16,8) [] = { 0x, 0x, 0x, 0x,
+0x, 0x, 0x, 0x };
+VECT_VAR_DECL(expected_vld2_0,uint,32,4) [] = { 0x, 0x,
+0x, 0x };
+VECT_VAR_DECL(expected_vld2_0,uint,64,2) [] = { 0x,
+0x };
+VECT_VAR_DECL(expected_vld2_0,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+0x33, 0x33, 0x33, 0x33,
+0x33, 0x33, 0x33, 0x33,
+0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld2_0,poly,16,8) [] = { 0x, 0x, 0x, 0x,
+0x, 0x, 0x, 0x };
+VECT_VAR_DECL(expected_vld2_0,hfloat,32,4) [] = { 0x, 0x,
+  0x, 0x };
+
+/* vld2_dup/chunk 1.  */
+VECT_VAR_DECL(expected_vld2_1,int,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
+ 0xf0, 0xf1, 0xf0, 0xf1 };
+VECT_VAR_DECL(expected_vld2_1,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff0, 0xfff1 
};
+VECT_VAR_DECL(expected_vld2_1,int,32,2) [] = { 0xfff0, 0xfff1 };
+VECT_VAR_DECL(expected_vld2_1,int,64,1) [] = { 0xfff1 };
+VECT_VAR_DECL(expected_vld2_1,uint,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
+  0xf0, 0xf1, 0xf0, 0xf1 };
+VECT_VAR_DECL(expected_vld2_1,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff0, 0xfff1 
};
+VECT_VAR_DECL(expected_vld2_1,uint,32,2) [] = { 0xfff0, 0xfff1 };
+VECT_VAR_DECL(expected_vld2_1,uint,64,1) [] = { 0xfff1 };
+VECT_VAR_DECL(expected_vld2_1,poly,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
+  0xf0, 0xf1, 0xf0, 0xf1 };
+VECT_VAR_DECL(expected_vld2_1,poly,16,4) [] = { 0xfff0, 0xfff1,
+   0xfff0, 0xfff1 };
+VECT_VAR_DECL(expected_vld2_1,hfloat,32,2) [] = { 0xc180, 0xc170 };
+VECT_VAR_DECL(expected_vld2_1,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+  0x33, 0x33, 0x33, 0x33,
+  0x33, 0x33, 0x33, 0x33,
+  0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld2_1,int,16,8) [] = { 0x, 0x,

Re: [[ARM/AArch64][testsuite] 05/36] Add vldX_dup test.

2015-01-16 Thread Christophe Lyon

On 16 January 2015 at 16:20, Tejas Belagod tejas.bela...@arm.com wrote:
 On 13/01/15 15:18, Christophe Lyon wrote:


  * gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c: New file.

 diff --git
 a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c
 b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c
 new file mode 100644
 index 000..53cd8f3
 --- /dev/null
 +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c
 @@ -0,0 +1,671 @@
 +#include arm_neon.h
 +#include arm-neon-ref.h
 +#include compute-ref-data.h
 +
 +/* Expected results.  */
 +
 +/* vld2_dup/chunk 0.  */
 +VECT_VAR_DECL(expected_vld2_0,int,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
 +  0xf0, 0xf1, 0xf0, 0xf1 };
 +VECT_VAR_DECL(expected_vld2_0,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff0,
 0xfff1 };
 +VECT_VAR_DECL(expected_vld2_0,int,32,2) [] = { 0xfff0, 0xfff1 };
 +VECT_VAR_DECL(expected_vld2_0,int,64,1) [] = { 0xfff0 };
 +VECT_VAR_DECL(expected_vld2_0,uint,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
 +   0xf0, 0xf1, 0xf0, 0xf1 };
 +VECT_VAR_DECL(expected_vld2_0,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff0,
 0xfff1 };
 +VECT_VAR_DECL(expected_vld2_0,uint,32,2) [] = { 0xfff0, 0xfff1 };
 +VECT_VAR_DECL(expected_vld2_0,uint,64,1) [] = { 0xfff0 };
 +VECT_VAR_DECL(expected_vld2_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
 +   0xf0, 0xf1, 0xf0, 0xf1 };
 +VECT_VAR_DECL(expected_vld2_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff0,
 0xfff1 };
 +VECT_VAR_DECL(expected_vld2_0,hfloat,32,2) [] = { 0xc180, 0xc170
 };
 +VECT_VAR_DECL(expected_vld2_0,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
 +   0x33, 0x33, 0x33, 0x33,
 +   0x33, 0x33, 0x33, 0x33,
 +   0x33, 0x33, 0x33, 0x33 };
 +VECT_VAR_DECL(expected_vld2_0,int,16,8) [] = { 0x, 0x, 0x,
 0x,
 +   0x, 0x, 0x, 0x };
 +VECT_VAR_DECL(expected_vld2_0,int,32,4) [] = { 0x, 0x,
 +   0x, 0x };
 +VECT_VAR_DECL(expected_vld2_0,int,64,2) [] = { 0x,
 +   0x };
 +VECT_VAR_DECL(expected_vld2_0,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
 +0x33, 0x33, 0x33, 0x33,
 +0x33, 0x33, 0x33, 0x33,
 +0x33, 0x33, 0x33, 0x33 };
 +VECT_VAR_DECL(expected_vld2_0,uint,16,8) [] = { 0x, 0x, 0x,
 0x,
 +0x, 0x, 0x, 0x };
 +VECT_VAR_DECL(expected_vld2_0,uint,32,4) [] = { 0x, 0x,
 +0x, 0x };
 +VECT_VAR_DECL(expected_vld2_0,uint,64,2) [] = { 0x,
 +0x };
 +VECT_VAR_DECL(expected_vld2_0,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
 +0x33, 0x33, 0x33, 0x33,
 +0x33, 0x33, 0x33, 0x33,
 +0x33, 0x33, 0x33, 0x33 };
 +VECT_VAR_DECL(expected_vld2_0,poly,16,8) [] = { 0x, 0x, 0x,
 0x,
 +0x, 0x, 0x, 0x };
 +VECT_VAR_DECL(expected_vld2_0,hfloat,32,4) [] = { 0x, 0x,
 +  0x, 0x };
 +
 +/* vld2_dup/chunk 1.  */
 +VECT_VAR_DECL(expected_vld2_1,int,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
 + 0xf0, 0xf1, 0xf0, 0xf1 };
 +VECT_VAR_DECL(expected_vld2_1,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff0,
 0xfff1 };
 +VECT_VAR_DECL(expected_vld2_1,int,32,2) [] = { 0xfff0, 0xfff1 };
 +VECT_VAR_DECL(expected_vld2_1,int,64,1) [] = { 0xfff1 };
 +VECT_VAR_DECL(expected_vld2_1,uint,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
 +  0xf0, 0xf1, 0xf0, 0xf1 };
 +VECT_VAR_DECL(expected_vld2_1,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff0,
 0xfff1 };
 +VECT_VAR_DECL(expected_vld2_1,uint,32,2) [] = { 0xfff0, 0xfff1 };
 +VECT_VAR_DECL(expected_vld2_1,uint,64,1) [] = { 0xfff1 };
 +VECT_VAR_DECL(expected_vld2_1,poly,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
 +  0xf0, 0xf1, 0xf0, 0xf1 };
 +VECT_VAR_DECL(expected_vld2_1,poly,16,4) [] = { 0xfff0, 0xfff1,
 +   0xfff0, 0xfff1 };
 +VECT_VAR_DECL(expected_vld2_1,hfloat,32,2) [] = { 0xc180, 0xc170
 };
 +VECT_VAR_DECL(expected_vld2_1,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
 +  0x33, 0x33, 0x33, 0x33,
 +  0x33,

[[ARM/AArch64][testsuite] 05/36] Add vldX_dup test.

2015-01-13 Thread Christophe Lyon


* gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c: New file.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c 
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c
new file mode 100644
index 000..53cd8f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c
@@ -0,0 +1,671 @@
+#include arm_neon.h
+#include arm-neon-ref.h
+#include compute-ref-data.h
+
+/* Expected results.  */
+
+/* vld2_dup/chunk 0.  */
+VECT_VAR_DECL(expected_vld2_0,int,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
+  0xf0, 0xf1, 0xf0, 0xf1 };
+VECT_VAR_DECL(expected_vld2_0,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff0, 0xfff1 
};
+VECT_VAR_DECL(expected_vld2_0,int,32,2) [] = { 0xfff0, 0xfff1 };
+VECT_VAR_DECL(expected_vld2_0,int,64,1) [] = { 0xfff0 };
+VECT_VAR_DECL(expected_vld2_0,uint,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
+   0xf0, 0xf1, 0xf0, 0xf1 };
+VECT_VAR_DECL(expected_vld2_0,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff0, 0xfff1 
};
+VECT_VAR_DECL(expected_vld2_0,uint,32,2) [] = { 0xfff0, 0xfff1 };
+VECT_VAR_DECL(expected_vld2_0,uint,64,1) [] = { 0xfff0 };
+VECT_VAR_DECL(expected_vld2_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
+   0xf0, 0xf1, 0xf0, 0xf1 };
+VECT_VAR_DECL(expected_vld2_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff0, 0xfff1 
};
+VECT_VAR_DECL(expected_vld2_0,hfloat,32,2) [] = { 0xc180, 0xc170 };
+VECT_VAR_DECL(expected_vld2_0,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+   0x33, 0x33, 0x33, 0x33,
+   0x33, 0x33, 0x33, 0x33,
+   0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld2_0,int,16,8) [] = { 0x, 0x, 0x, 0x,
+   0x, 0x, 0x, 0x };
+VECT_VAR_DECL(expected_vld2_0,int,32,4) [] = { 0x, 0x,
+   0x, 0x };
+VECT_VAR_DECL(expected_vld2_0,int,64,2) [] = { 0x,
+   0x };
+VECT_VAR_DECL(expected_vld2_0,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+0x33, 0x33, 0x33, 0x33,
+0x33, 0x33, 0x33, 0x33,
+0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld2_0,uint,16,8) [] = { 0x, 0x, 0x, 0x,
+0x, 0x, 0x, 0x };
+VECT_VAR_DECL(expected_vld2_0,uint,32,4) [] = { 0x, 0x,
+0x, 0x };
+VECT_VAR_DECL(expected_vld2_0,uint,64,2) [] = { 0x,
+0x };
+VECT_VAR_DECL(expected_vld2_0,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+0x33, 0x33, 0x33, 0x33,
+0x33, 0x33, 0x33, 0x33,
+0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld2_0,poly,16,8) [] = { 0x, 0x, 0x, 0x,
+0x, 0x, 0x, 0x };
+VECT_VAR_DECL(expected_vld2_0,hfloat,32,4) [] = { 0x, 0x,
+  0x, 0x };
+
+/* vld2_dup/chunk 1.  */
+VECT_VAR_DECL(expected_vld2_1,int,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
+ 0xf0, 0xf1, 0xf0, 0xf1 };
+VECT_VAR_DECL(expected_vld2_1,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff0, 0xfff1 
};
+VECT_VAR_DECL(expected_vld2_1,int,32,2) [] = { 0xfff0, 0xfff1 };
+VECT_VAR_DECL(expected_vld2_1,int,64,1) [] = { 0xfff1 };
+VECT_VAR_DECL(expected_vld2_1,uint,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
+  0xf0, 0xf1, 0xf0, 0xf1 };
+VECT_VAR_DECL(expected_vld2_1,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff0, 0xfff1 
};
+VECT_VAR_DECL(expected_vld2_1,uint,32,2) [] = { 0xfff0, 0xfff1 };
+VECT_VAR_DECL(expected_vld2_1,uint,64,1) [] = { 0xfff1 };
+VECT_VAR_DECL(expected_vld2_1,poly,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
+  0xf0, 0xf1, 0xf0, 0xf1 };
+VECT_VAR_DECL(expected_vld2_1,poly,16,4) [] = { 0xfff0, 0xfff1,
+   0xfff0, 0xfff1 };
+VECT_VAR_DECL(expected_vld2_1,hfloat,32,2) [] = { 0xc180, 0xc170 };
+VECT_VAR_DECL(expected_vld2_1,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+  0x33, 0x33, 0x33, 0x33,
+  0x33, 0x33, 0x33, 0x33,
+  0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld2_1,int,16,8) [] = { 0x, 0x, 0x, 0x,
+

Re: [[ARM/AArch64][testsuite] 05/36] Add vldX_dup test.

Re: [[ARM/AArch64][testsuite] 05/36] Add vldX_dup test.

Re: [[ARM/AArch64][testsuite] 05/36] Add vldX_dup test.

Re: [[ARM/AArch64][testsuite] 05/36] Add vldX_dup test.

Re: [[ARM/AArch64][testsuite] 05/36] Add vldX_dup test.

[[ARM/AArch64][testsuite] 05/36] Add vldX_dup test.

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