Re: [[ARM/AArch64][testsuite] 08/36] Add vtrn tests. Refactor vzup and vzip tests.

2015-01-19 Thread Marcus Shawcroft 
On 16 January 2015 at 18:10, Christophe Lyon  wrote:
> On 16 January 2015 at 16:58, Tejas Belagod  wrote:
>> On 13/01/15 15:18, Christophe Lyon wrote:

>>>  * gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc: New file.
>>>  * gcc.target/aarch64/advsimd-intrinsics/vtrn.c: New file.
>>>  * gcc.target/aarch64/advsimd-intrinsics/vuzp.c: Use code from
>>>  vshuffle.inc.
>>>  * gcc.target/aarch64/advsimd-intrinsics/vzip.c: Use code from
>>>  vshuffle.inc.

>>
>> LGTM.
>>
> Thanks, I should mention that the new vtrn test fails on aarch64_be
> (like vzip and vuzp), because of pending Alan's patches to fix
> aarch64_be load/stores.
> So strictly speaking this patch show new fails.
>

OK /Marcus

Re: [[ARM/AArch64][testsuite] 08/36] Add vtrn tests. Refactor vzup and vzip tests.

2015-01-16 Thread Christophe Lyon 
On 16 January 2015 at 16:58, Tejas Belagod  wrote:
> On 13/01/15 15:18, Christophe Lyon wrote:
>>
>>
>>  * gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc: New file.
>>  * gcc.target/aarch64/advsimd-intrinsics/vtrn.c: New file.
>>  * gcc.target/aarch64/advsimd-intrinsics/vuzp.c: Use code from
>>  vshuffle.inc.
>>  * gcc.target/aarch64/advsimd-intrinsics/vzip.c: Use code from
>>  vshuffle.inc.
>>
>> diff --git
>> a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc
>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc
>> new file mode 100644
>> index 000..928f338
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc
>> @@ -0,0 +1,139 @@
>> +#define FNNAME1(NAME) exec_ ## NAME
>> +#define FNNAME(NAME) FNNAME1(NAME)
>> +
>> +void FNNAME (INSN_NAME) (void)
>> +{
>> +  /* In this case, output variables are arrays of vectors.  */
>> +#define DECL_VSHUFFLE(T1, W, N)
>> \
>> +  VECT_ARRAY_TYPE(T1, W, N, 2) VECT_ARRAY_VAR(result_vec, T1, W, N, 2);
>> \
>> +  VECT_VAR_DECL(result_bis, T1, W, N)[2 * N]
>> +
>> +  /* We need to use a temporary result buffer (result_bis), because
>> + the one used for other tests is not large enough. A subset of the
>> + result data is moved from result_bis to result, and it is this
>> + subset which is used to check the actual behaviour. The next
>> + macro enables to move another chunk of data from result_bis to
>> + result.  */
>> +#define TEST_VSHUFFLE(INSN, Q, T1, T2, W, N)   \
>> +  VECT_ARRAY_VAR(result_vec, T1, W, N, 2) =\
>> +INSN##Q##_##T2##W(VECT_VAR(vector1, T1, W, N), \
>> + VECT_VAR(vector2, T1, W, N)); \
>> +  vst2##Q##_##T2##W(VECT_VAR(result_bis, T1, W, N),\
>> +   VECT_ARRAY_VAR(result_vec, T1, W, N, 2));   \
>> +  memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(result_bis, T1, W, N),   \
>> +sizeof(VECT_VAR(result, T1, W, N)));
>> +
>> +  /* Overwrite "result" with the contents of "result_bis"[X].  */
>> +#define TEST_EXTRA_CHUNK(T1, W, N, X)  \
>> +  memcpy(VECT_VAR(result, T1, W, N), &(VECT_VAR(result_bis, T1, W,
>> N)[X*N]), \
>> +sizeof(VECT_VAR(result, T1, W, N)));
>> +
>> +  DECL_VARIABLE_ALL_VARIANTS(vector1);
>> +  DECL_VARIABLE_ALL_VARIANTS(vector2);
>> +
>> +  /* We don't need 64 bits variants.  */
>> +#define DECL_ALL_VSHUFFLE()\
>> +  DECL_VSHUFFLE(int, 8, 8);\
>> +  DECL_VSHUFFLE(int, 16, 4);   \
>> +  DECL_VSHUFFLE(int, 32, 2);   \
>> +  DECL_VSHUFFLE(uint, 8, 8);   \
>> +  DECL_VSHUFFLE(uint, 16, 4);  \
>> +  DECL_VSHUFFLE(uint, 32, 2);  \
>> +  DECL_VSHUFFLE(poly, 8, 8);   \
>> +  DECL_VSHUFFLE(poly, 16, 4);  \
>> +  DECL_VSHUFFLE(float, 32, 2); \
>> +  DECL_VSHUFFLE(int, 8, 16);   \
>> +  DECL_VSHUFFLE(int, 16, 8);   \
>> +  DECL_VSHUFFLE(int, 32, 4);   \
>> +  DECL_VSHUFFLE(uint, 8, 16);  \
>> +  DECL_VSHUFFLE(uint, 16, 8);  \
>> +  DECL_VSHUFFLE(uint, 32, 4);  \
>> +  DECL_VSHUFFLE(poly, 8, 16);  \
>> +  DECL_VSHUFFLE(poly, 16, 8);  \
>> +  DECL_VSHUFFLE(float, 32, 4)
>> +
>> +  DECL_ALL_VSHUFFLE();
>> +
>> +  /* Initialize input "vector" from "buffer".  */
>> +  TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector1, buffer);
>> +  VLOAD(vector1, buffer, , float, f, 32, 2);
>> +  VLOAD(vector1, buffer, q, float, f, 32, 4);
>> +
>> +  /* Choose arbitrary initialization values.  */
>> +  VDUP(vector2, , int, s, 8, 8, 0x11);
>> +  VDUP(vector2, , int, s, 16, 4, 0x22);
>> +  VDUP(vector2, , int, s, 32, 2, 0x33);
>> +  VDUP(vector2, , uint, u, 8, 8, 0x55);
>> +  VDUP(vector2, , uint, u, 16, 4, 0x66);
>> +  VDUP(vector2, , uint, u, 32, 2, 0x77);
>> +  VDUP(vector2, , poly, p, 8, 8, 0x55);
>> +  VDUP(vector2, , poly, p, 16, 4, 0x66);
>> +  VDUP(vector2, , float, f, 32, 2, 33.6f);
>> +
>> +  VDUP(vector2, q, int, s, 8, 16, 0x11);
>> +  VDUP(vector2, q, int, s, 16, 8, 0x22);
>> +  VDUP(vector2, q, int, s, 32, 4, 0x33);
>> +  VDUP(vector2, q, uint, u, 8, 16, 0x55);
>> +  VDUP(vector2, q, uint, u, 16, 8, 0x66);
>> +  VDUP(vector2, q, uint, u, 32, 4, 0x77);
>> +  VDUP(vector2, q, poly, p, 8, 16, 0x55);
>> +  VDUP(vector2, q, poly, p, 16, 8, 0x66);
>> +  VDUP(vector2, q, float, f, 32, 4, 33.8f);
>> +
>> +#define TEST_ALL_VSHUFFLE(INSN)\
>> +  TEST_VSHUFFLE(INSN, , int, s, 8, 8); \
>> +  TEST_VSHUFFLE(INSN, , int, s, 16, 4);\
>> +

Re: [[ARM/AArch64][testsuite] 08/36] Add vtrn tests. Refactor vzup and vzip tests.

2015-01-16 Thread Tejas Belagod 

On 13/01/15 15:18, Christophe Lyon wrote:


 * gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc: New file.
 * gcc.target/aarch64/advsimd-intrinsics/vtrn.c: New file.
 * gcc.target/aarch64/advsimd-intrinsics/vuzp.c: Use code from
 vshuffle.inc.
 * gcc.target/aarch64/advsimd-intrinsics/vzip.c: Use code from
 vshuffle.inc.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc 
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc
new file mode 100644
index 000..928f338
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc
@@ -0,0 +1,139 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+  /* In this case, output variables are arrays of vectors.  */
+#define DECL_VSHUFFLE(T1, W, N)
\
+  VECT_ARRAY_TYPE(T1, W, N, 2) VECT_ARRAY_VAR(result_vec, T1, W, N, 2);
\
+  VECT_VAR_DECL(result_bis, T1, W, N)[2 * N]
+
+  /* We need to use a temporary result buffer (result_bis), because
+ the one used for other tests is not large enough. A subset of the
+ result data is moved from result_bis to result, and it is this
+ subset which is used to check the actual behaviour. The next
+ macro enables to move another chunk of data from result_bis to
+ result.  */
+#define TEST_VSHUFFLE(INSN, Q, T1, T2, W, N)   \
+  VECT_ARRAY_VAR(result_vec, T1, W, N, 2) =\
+INSN##Q##_##T2##W(VECT_VAR(vector1, T1, W, N), \
+ VECT_VAR(vector2, T1, W, N)); \
+  vst2##Q##_##T2##W(VECT_VAR(result_bis, T1, W, N),\
+   VECT_ARRAY_VAR(result_vec, T1, W, N, 2));   \
+  memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(result_bis, T1, W, N),   \
+sizeof(VECT_VAR(result, T1, W, N)));
+
+  /* Overwrite "result" with the contents of "result_bis"[X].  */
+#define TEST_EXTRA_CHUNK(T1, W, N, X)  \
+  memcpy(VECT_VAR(result, T1, W, N), &(VECT_VAR(result_bis, T1, W, N)[X*N]), \
+sizeof(VECT_VAR(result, T1, W, N)));
+
+  DECL_VARIABLE_ALL_VARIANTS(vector1);
+  DECL_VARIABLE_ALL_VARIANTS(vector2);
+
+  /* We don't need 64 bits variants.  */
+#define DECL_ALL_VSHUFFLE()\
+  DECL_VSHUFFLE(int, 8, 8);\
+  DECL_VSHUFFLE(int, 16, 4);   \
+  DECL_VSHUFFLE(int, 32, 2);   \
+  DECL_VSHUFFLE(uint, 8, 8);   \
+  DECL_VSHUFFLE(uint, 16, 4);  \
+  DECL_VSHUFFLE(uint, 32, 2);  \
+  DECL_VSHUFFLE(poly, 8, 8);   \
+  DECL_VSHUFFLE(poly, 16, 4);  \
+  DECL_VSHUFFLE(float, 32, 2); \
+  DECL_VSHUFFLE(int, 8, 16);   \
+  DECL_VSHUFFLE(int, 16, 8);   \
+  DECL_VSHUFFLE(int, 32, 4);   \
+  DECL_VSHUFFLE(uint, 8, 16);  \
+  DECL_VSHUFFLE(uint, 16, 8);  \
+  DECL_VSHUFFLE(uint, 32, 4);  \
+  DECL_VSHUFFLE(poly, 8, 16);  \
+  DECL_VSHUFFLE(poly, 16, 8);  \
+  DECL_VSHUFFLE(float, 32, 4)
+
+  DECL_ALL_VSHUFFLE();
+
+  /* Initialize input "vector" from "buffer".  */
+  TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector1, buffer);
+  VLOAD(vector1, buffer, , float, f, 32, 2);
+  VLOAD(vector1, buffer, q, float, f, 32, 4);
+
+  /* Choose arbitrary initialization values.  */
+  VDUP(vector2, , int, s, 8, 8, 0x11);
+  VDUP(vector2, , int, s, 16, 4, 0x22);
+  VDUP(vector2, , int, s, 32, 2, 0x33);
+  VDUP(vector2, , uint, u, 8, 8, 0x55);
+  VDUP(vector2, , uint, u, 16, 4, 0x66);
+  VDUP(vector2, , uint, u, 32, 2, 0x77);
+  VDUP(vector2, , poly, p, 8, 8, 0x55);
+  VDUP(vector2, , poly, p, 16, 4, 0x66);
+  VDUP(vector2, , float, f, 32, 2, 33.6f);
+
+  VDUP(vector2, q, int, s, 8, 16, 0x11);
+  VDUP(vector2, q, int, s, 16, 8, 0x22);
+  VDUP(vector2, q, int, s, 32, 4, 0x33);
+  VDUP(vector2, q, uint, u, 8, 16, 0x55);
+  VDUP(vector2, q, uint, u, 16, 8, 0x66);
+  VDUP(vector2, q, uint, u, 32, 4, 0x77);
+  VDUP(vector2, q, poly, p, 8, 16, 0x55);
+  VDUP(vector2, q, poly, p, 16, 8, 0x66);
+  VDUP(vector2, q, float, f, 32, 4, 33.8f);
+
+#define TEST_ALL_VSHUFFLE(INSN)\
+  TEST_VSHUFFLE(INSN, , int, s, 8, 8); \
+  TEST_VSHUFFLE(INSN, , int, s, 16, 4);\
+  TEST_VSHUFFLE(INSN, , int, s, 32, 2);\
+  TEST_VSHUFFLE(INSN, , uint, u, 8, 8);\
+  TEST_VSHUFFLE(INSN, , uint, u, 16, 4);   \
+  TEST_VSHUFFLE(INSN, , uint, u, 32, 2);   \
+  TEST_VSHUFFLE(INSN, , poly, p, 8, 8);

[[ARM/AArch64][testsuite] 08/36] Add vtrn tests. Refactor vzup and vzip tests.

2015-01-13 Thread Christophe Lyon 

* gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vtrn.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vuzp.c: Use code from
vshuffle.inc.
* gcc.target/aarch64/advsimd-intrinsics/vzip.c: Use code from
vshuffle.inc.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc 
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc
new file mode 100644
index 000..928f338
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc
@@ -0,0 +1,139 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+  /* In this case, output variables are arrays of vectors.  */
+#define DECL_VSHUFFLE(T1, W, N)
\
+  VECT_ARRAY_TYPE(T1, W, N, 2) VECT_ARRAY_VAR(result_vec, T1, W, N, 2);
\
+  VECT_VAR_DECL(result_bis, T1, W, N)[2 * N]
+
+  /* We need to use a temporary result buffer (result_bis), because
+ the one used for other tests is not large enough. A subset of the
+ result data is moved from result_bis to result, and it is this
+ subset which is used to check the actual behaviour. The next
+ macro enables to move another chunk of data from result_bis to
+ result.  */
+#define TEST_VSHUFFLE(INSN, Q, T1, T2, W, N)   \
+  VECT_ARRAY_VAR(result_vec, T1, W, N, 2) =\
+INSN##Q##_##T2##W(VECT_VAR(vector1, T1, W, N), \
+ VECT_VAR(vector2, T1, W, N)); \
+  vst2##Q##_##T2##W(VECT_VAR(result_bis, T1, W, N),\
+   VECT_ARRAY_VAR(result_vec, T1, W, N, 2));   \
+  memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(result_bis, T1, W, N),   \
+sizeof(VECT_VAR(result, T1, W, N)));
+
+  /* Overwrite "result" with the contents of "result_bis"[X].  */
+#define TEST_EXTRA_CHUNK(T1, W, N, X)  \
+  memcpy(VECT_VAR(result, T1, W, N), &(VECT_VAR(result_bis, T1, W, N)[X*N]), \
+sizeof(VECT_VAR(result, T1, W, N)));
+
+  DECL_VARIABLE_ALL_VARIANTS(vector1);
+  DECL_VARIABLE_ALL_VARIANTS(vector2);
+
+  /* We don't need 64 bits variants.  */
+#define DECL_ALL_VSHUFFLE()\
+  DECL_VSHUFFLE(int, 8, 8);\
+  DECL_VSHUFFLE(int, 16, 4);   \
+  DECL_VSHUFFLE(int, 32, 2);   \
+  DECL_VSHUFFLE(uint, 8, 8);   \
+  DECL_VSHUFFLE(uint, 16, 4);  \
+  DECL_VSHUFFLE(uint, 32, 2);  \
+  DECL_VSHUFFLE(poly, 8, 8);   \
+  DECL_VSHUFFLE(poly, 16, 4);  \
+  DECL_VSHUFFLE(float, 32, 2); \
+  DECL_VSHUFFLE(int, 8, 16);   \
+  DECL_VSHUFFLE(int, 16, 8);   \
+  DECL_VSHUFFLE(int, 32, 4);   \
+  DECL_VSHUFFLE(uint, 8, 16);  \
+  DECL_VSHUFFLE(uint, 16, 8);  \
+  DECL_VSHUFFLE(uint, 32, 4);  \
+  DECL_VSHUFFLE(poly, 8, 16);  \
+  DECL_VSHUFFLE(poly, 16, 8);  \
+  DECL_VSHUFFLE(float, 32, 4)
+
+  DECL_ALL_VSHUFFLE();
+
+  /* Initialize input "vector" from "buffer".  */
+  TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector1, buffer);
+  VLOAD(vector1, buffer, , float, f, 32, 2);
+  VLOAD(vector1, buffer, q, float, f, 32, 4);
+
+  /* Choose arbitrary initialization values.  */
+  VDUP(vector2, , int, s, 8, 8, 0x11);
+  VDUP(vector2, , int, s, 16, 4, 0x22);
+  VDUP(vector2, , int, s, 32, 2, 0x33);
+  VDUP(vector2, , uint, u, 8, 8, 0x55);
+  VDUP(vector2, , uint, u, 16, 4, 0x66);
+  VDUP(vector2, , uint, u, 32, 2, 0x77);
+  VDUP(vector2, , poly, p, 8, 8, 0x55);
+  VDUP(vector2, , poly, p, 16, 4, 0x66);
+  VDUP(vector2, , float, f, 32, 2, 33.6f);
+
+  VDUP(vector2, q, int, s, 8, 16, 0x11);
+  VDUP(vector2, q, int, s, 16, 8, 0x22);
+  VDUP(vector2, q, int, s, 32, 4, 0x33);
+  VDUP(vector2, q, uint, u, 8, 16, 0x55);
+  VDUP(vector2, q, uint, u, 16, 8, 0x66);
+  VDUP(vector2, q, uint, u, 32, 4, 0x77);
+  VDUP(vector2, q, poly, p, 8, 16, 0x55);
+  VDUP(vector2, q, poly, p, 16, 8, 0x66);
+  VDUP(vector2, q, float, f, 32, 4, 33.8f);
+  
+#define TEST_ALL_VSHUFFLE(INSN)\
+  TEST_VSHUFFLE(INSN, , int, s, 8, 8); \
+  TEST_VSHUFFLE(INSN, , int, s, 16, 4);\
+  TEST_VSHUFFLE(INSN, , int, s, 32, 2);\
+  TEST_VSHUFFLE(INSN, , uint, u, 8, 8);\
+  TEST_VSHUFFLE(INSN, , uint, u, 16, 4);   \
+  TEST_VSHUFFLE(INSN, , uint, u, 32, 2);   \
+  TEST_VSHUFFLE(INSN, , poly, p, 8, 8);\
+  TEST_VSHUFFLE(INSN, , poly, p, 16, 4);