Re: [[ARM/AArch64][testsuite] 09/36] Add vsubhn, vraddhn and vrsubhn tests. Split vaddhn.c into vXXXhn.inc and vaddhn.c to share code with other new tests.
On 20 January 2015 at 15:24, Christophe Lyon christophe.l...@linaro.org wrote: Here is an updated version, where I have removed a few more useless variables than you noticed: the [u]int64x1 as well as the 128 bits ones. OK /Marcus
Re: [[ARM/AArch64][testsuite] 09/36] Add vsubhn, vraddhn and vrsubhn tests. Split vaddhn.c into vXXXhn.inc and vaddhn.c to share code with other new tests.
On 16 January 2015 at 17:30, Christophe Lyon christophe.l...@linaro.org wrote:
On 16 January 2015 at 17:07, Tejas Belagod tejas.bela...@arm.com wrote:
On 13/01/15 15:18, Christophe Lyon wrote:
* gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vraddhn.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vrsubhn.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vsubhn.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vaddhn.c: Use code from
vXXXhn.inc.
diff --git
a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc
new file mode 100644
index 000..0dbcc92
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc
@@ -0,0 +1,50 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ /* Basic test: vec64=vaddhn(vec128_a, vec128_b), then store the result.
*/
+#define TEST_VADDHN1(INSN, T1, T2, W, W2, N) \
+ VECT_VAR(vector64, T1, W2, N) = INSN##_##T2##W(VECT_VAR(vector1, T1, W,
N), \
+VECT_VAR(vector2, T1, W,
N)); \
+ vst1_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector64, T1, W2,
N))
+
+#define TEST_VADDHN(INSN, T1, T2, W, W2, N)\
+ TEST_VADDHN1(INSN, T1, T2, W, W2, N)
+
Minor nit. If this is a template file, maybe you should name this macro
TEST_ADDHN as TEST_XXHN? Just that a template having an INSN name is
confusing.
Agreed.
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0x, 0x, 0x, 0x
};
Though never used, poly seems to have sneaked in here too.
Indeed, sorry for that.
I rushed to have as many tests as possible ready before stage 4, but
obviously I missed a few cleanups.
Here is an updated version, where I have removed a few more useless
variables than you noticed: the [u]int64x1 as well as the 128 bits
ones.
Christophe.
Otherwise, LGTM.
Thanks,
Tejas.
From 3acafe49a7402b859a88d1ef808b828a0acf96c4 Mon Sep 17 00:00:00 2001
From: Christophe Lyon christophe.l...@linaro.org
Date: Tue, 2 Dec 2014 15:05:30 +0100
Subject: [[ARM/AArch64][testsuite] 09/36] Add vsubhn, vraddhn and vrsubhn
tests. Split vaddhn.c into vXXXhn.inc and vaddhn.c to share code with other
new tests.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc
new file mode 100644
index 000..5aabedd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc
@@ -0,0 +1,55 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ /* Basic test: vec64=vXXXhn(vec128_a, vec128_b), then store the result. */
+#define TEST_VXXXHN1(INSN, T1, T2, W, W2, N)\
+ VECT_VAR(vector64, T1, W2, N) = INSN##_##T2##W(VECT_VAR(vector1, T1, W, N), \
+ VECT_VAR(vector2, T1, W, N)); \
+ vst1_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector64, T1, W2, N))
+
+#define TEST_VXXXHN(INSN, T1, T2, W, W2, N) \
+ TEST_VXXXHN1(INSN, T1, T2, W, W2, N)
+
+ DECL_VARIABLE_64BITS_VARIANTS(vector64);
+ DECL_VARIABLE_128BITS_VARIANTS(vector1);
+ DECL_VARIABLE_128BITS_VARIANTS(vector2);
+
+ clean_results ();
+
+ /* Fill input vector1 and vector2 with arbitrary values */
+ VDUP(vector1, q, int, s, 16, 8, 50*(UINT8_MAX+1));
+ VDUP(vector1, q, int, s, 32, 4, 50*(UINT16_MAX+1));
+ VDUP(vector1, q, int, s, 64, 2, 24*((uint64_t)UINT32_MAX+1));
+ VDUP(vector1, q, uint, u, 16, 8, 3*(UINT8_MAX+1));
+ VDUP(vector1, q, uint, u, 32, 4, 55*(UINT16_MAX+1));
+ VDUP(vector1, q, uint, u, 64, 2, 3*((uint64_t)UINT32_MAX+1));
+
+ VDUP(vector2, q, int, s, 16, 8, (uint16_t)UINT8_MAX);
+ VDUP(vector2, q, int, s, 32, 4, (uint32_t)UINT16_MAX);
+ VDUP(vector2, q, int, s, 64, 2, (uint64_t)UINT32_MAX);
+ VDUP(vector2, q, uint, u, 16, 8, (uint16_t)UINT8_MAX);
+ VDUP(vector2, q, uint, u, 32, 4, (uint32_t)UINT16_MAX);
+ VDUP(vector2, q, uint, u, 64, 2, (uint64_t)UINT32_MAX);
+
+ TEST_VXXXHN(INSN_NAME, int, s, 16, 8, 8);
+ TEST_VXXXHN(INSN_NAME, int, s, 32, 16, 4);
+ TEST_VXXXHN(INSN_NAME, int, s, 64, 32, 2);
+ TEST_VXXXHN(INSN_NAME, uint, u, 16, 8, 8);
+ TEST_VXXXHN(INSN_NAME, uint, u, 32, 16, 4);
+ TEST_VXXXHN(INSN_NAME, uint, u, 64, 32, 2);
+
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, );
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, );
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, );
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, );
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, );
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, );
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
diff --git
Re: [[ARM/AArch64][testsuite] 09/36] Add vsubhn, vraddhn and vrsubhn tests. Split vaddhn.c into vXXXhn.inc and vaddhn.c to share code with other new tests.
On 13/01/15 15:18, Christophe Lyon wrote:
* gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vraddhn.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vrsubhn.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vsubhn.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vaddhn.c: Use code from
vXXXhn.inc.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc
new file mode 100644
index 000..0dbcc92
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc
@@ -0,0 +1,50 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ /* Basic test: vec64=vaddhn(vec128_a, vec128_b), then store the result. */
+#define TEST_VADDHN1(INSN, T1, T2, W, W2, N) \
+ VECT_VAR(vector64, T1, W2, N) = INSN##_##T2##W(VECT_VAR(vector1, T1, W, N), \
+VECT_VAR(vector2, T1, W, N)); \
+ vst1_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector64, T1, W2, N))
+
+#define TEST_VADDHN(INSN, T1, T2, W, W2, N)\
+ TEST_VADDHN1(INSN, T1, T2, W, W2, N)
+
Minor nit. If this is a template file, maybe you should name this macro
TEST_ADDHN as TEST_XXHN? Just that a template having an INSN name is
confusing.
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0x, 0x, 0x, 0x };
Though never used, poly seems to have sneaked in here too.
Otherwise, LGTM.
Thanks,
Tejas.
Re: [[ARM/AArch64][testsuite] 09/36] Add vsubhn, vraddhn and vrsubhn tests. Split vaddhn.c into vXXXhn.inc and vaddhn.c to share code with other new tests.
On 16 January 2015 at 17:07, Tejas Belagod tejas.bela...@arm.com wrote:
On 13/01/15 15:18, Christophe Lyon wrote:
* gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vraddhn.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vrsubhn.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vsubhn.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vaddhn.c: Use code from
vXXXhn.inc.
diff --git
a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc
new file mode 100644
index 000..0dbcc92
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc
@@ -0,0 +1,50 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ /* Basic test: vec64=vaddhn(vec128_a, vec128_b), then store the result.
*/
+#define TEST_VADDHN1(INSN, T1, T2, W, W2, N) \
+ VECT_VAR(vector64, T1, W2, N) = INSN##_##T2##W(VECT_VAR(vector1, T1, W,
N), \
+VECT_VAR(vector2, T1, W,
N)); \
+ vst1_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector64, T1, W2,
N))
+
+#define TEST_VADDHN(INSN, T1, T2, W, W2, N)\
+ TEST_VADDHN1(INSN, T1, T2, W, W2, N)
+
Minor nit. If this is a template file, maybe you should name this macro
TEST_ADDHN as TEST_XXHN? Just that a template having an INSN name is
confusing.
Agreed.
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0x, 0x, 0x, 0x
};
Though never used, poly seems to have sneaked in here too.
Indeed, sorry for that.
I rushed to have as many tests as possible ready before stage 4, but
obviously I missed a few cleanups.
Otherwise, LGTM.
Thanks,
Tejas.
[[ARM/AArch64][testsuite] 09/36] Add vsubhn, vraddhn and vrsubhn tests. Split vaddhn.c into vXXXhn.inc and vaddhn.c to share code with other new tests.
* gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vraddhn.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vrsubhn.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vsubhn.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vaddhn.c: Use code from
vXXXhn.inc.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc
new file mode 100644
index 000..0dbcc92
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc
@@ -0,0 +1,50 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ /* Basic test: vec64=vaddhn(vec128_a, vec128_b), then store the result. */
+#define TEST_VADDHN1(INSN, T1, T2, W, W2, N) \
+ VECT_VAR(vector64, T1, W2, N) = INSN##_##T2##W(VECT_VAR(vector1, T1, W, N), \
+VECT_VAR(vector2, T1, W, N)); \
+ vst1_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector64, T1, W2, N))
+
+#define TEST_VADDHN(INSN, T1, T2, W, W2, N)\
+ TEST_VADDHN1(INSN, T1, T2, W, W2, N)
+
+ DECL_VARIABLE_64BITS_VARIANTS(vector64);
+ DECL_VARIABLE_128BITS_VARIANTS(vector1);
+ DECL_VARIABLE_128BITS_VARIANTS(vector2);
+
+ clean_results ();
+
+ /* Fill input vector1 and vector2 with arbitrary values */
+ VDUP(vector1, q, int, s, 16, 8, 50*(UINT8_MAX+1));
+ VDUP(vector1, q, int, s, 32, 4, 50*(UINT16_MAX+1));
+ VDUP(vector1, q, int, s, 64, 2, 24*((uint64_t)UINT32_MAX+1));
+ VDUP(vector1, q, uint, u, 16, 8, 3*(UINT8_MAX+1));
+ VDUP(vector1, q, uint, u, 32, 4, 55*(UINT16_MAX+1));
+ VDUP(vector1, q, uint, u, 64, 2, 3*((uint64_t)UINT32_MAX+1));
+
+ VDUP(vector2, q, int, s, 16, 8, (uint16_t)UINT8_MAX);
+ VDUP(vector2, q, int, s, 32, 4, (uint32_t)UINT16_MAX);
+ VDUP(vector2, q, int, s, 64, 2, (uint64_t)UINT32_MAX);
+ VDUP(vector2, q, uint, u, 16, 8, (uint16_t)UINT8_MAX);
+ VDUP(vector2, q, uint, u, 32, 4, (uint32_t)UINT16_MAX);
+ VDUP(vector2, q, uint, u, 64, 2, (uint64_t)UINT32_MAX);
+
+ TEST_VADDHN(INSN_NAME, int, s, 16, 8, 8);
+ TEST_VADDHN(INSN_NAME, int, s, 32, 16, 4);
+ TEST_VADDHN(INSN_NAME, int, s, 64, 32, 2);
+ TEST_VADDHN(INSN_NAME, uint, u, 16, 8, 8);
+ TEST_VADDHN(INSN_NAME, uint, u, 32, 16, 4);
+ TEST_VADDHN(INSN_NAME, uint, u, 64, 32, 2);
+
+ CHECK_RESULTS (TEST_MSG, );
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddhn.c
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddhn.c
index 58fd5ea..88c92f3 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddhn.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddhn.c
@@ -8,6 +8,9 @@
#include stdint.h
#endif
+#define INSN_NAME vaddhn
+#define TEST_MSG VADDHN
+
/* Expected results. */
VECT_VAR_DECL(expected,int,8,8) [] = { 0x32, 0x32, 0x32, 0x32,
0x32, 0x32, 0x32, 0x32 };
@@ -52,56 +55,4 @@ VECT_VAR_DECL(expected,poly,16,8) [] = { 0x, 0x,
0x, 0x,
VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x, 0x,
0x, 0x };
-#define INSN_NAME vaddhn
-#define TEST_MSG VADDHN
-
-#define FNNAME1(NAME) exec_ ## NAME
-#define FNNAME(NAME) FNNAME1(NAME)
-
-void FNNAME (INSN_NAME) (void)
-{
- /* Basic test: vec64=vaddhn(vec128_a, vec128_b), then store the result. */
-#define TEST_VADDHN1(INSN, T1, T2, W, W2, N) \
- VECT_VAR(vector64, T1, W2, N) = INSN##_##T2##W(VECT_VAR(vector1, T1, W, N), \
-VECT_VAR(vector2, T1, W, N)); \
- vst1_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector64, T1, W2, N))
-
-#define TEST_VADDHN(INSN, T1, T2, W, W2, N)\
- TEST_VADDHN1(INSN, T1, T2, W, W2, N)
-
- DECL_VARIABLE_64BITS_VARIANTS(vector64);
- DECL_VARIABLE_128BITS_VARIANTS(vector1);
- DECL_VARIABLE_128BITS_VARIANTS(vector2);
-
- clean_results ();
-
- /* Fill input vector1 and vector2 with arbitrary values */
- VDUP(vector1, q, int, s, 16, 8, 50*(UINT8_MAX+1));
- VDUP(vector1, q, int, s, 32, 4, 50*(UINT16_MAX+1));
- VDUP(vector1, q, int, s, 64, 2, 24*((uint64_t)UINT32_MAX+1));
- VDUP(vector1, q, uint, u, 16, 8, 3*(UINT8_MAX+1));
- VDUP(vector1, q, uint, u, 32, 4, 55*(UINT16_MAX+1));
- VDUP(vector1, q, uint, u, 64, 2, 3*((uint64_t)UINT32_MAX+1));
-
- VDUP(vector2, q, int, s, 16, 8, (uint16_t)UINT8_MAX);
- VDUP(vector2, q, int, s, 32, 4, (uint32_t)UINT16_MAX);
- VDUP(vector2, q, int, s, 64, 2, (uint64_t)UINT32_MAX);
- VDUP(vector2, q, uint, u, 16, 8, (uint16_t)UINT8_MAX);
- VDUP(vector2, q, uint, u, 32, 4, (uint32_t)UINT16_MAX);
- VDUP(vector2, q, uint, u, 64, 2, (uint64_t)UINT32_MAX);
-
- TEST_VADDHN(INSN_NAME, int, s, 16, 8, 8);
- TEST_VADDHN(INSN_NAME, int, s, 32, 16, 4);
