Re: [Aarch64][3/3] Add tests for atomic compare-and-swap instructions.

2015-08-12 Thread James Greenhalgh
On Wed, Aug 12, 2015 at 11:16:41AM +0100, Matthew Wahab wrote:
> ARMv8.1 adds instructions for atomic compare-and-swap with optional
> memory ordering specifiers. This patch adds tests for the
> compare-and-swap instructions as two files. The first is support code to
> run the test with a range of types and memory models, the second is the
> test for the CAS instruction.
> 
> Tested the series for aarch64-none-linux-gnu with native bootstrap and make
> check and for aarch64-none-elf with cross-compiled check-gcc. Also tested
> aarch64-none-elf with cross-compiled check-gcc on an emulator that supports
> ARMv8.1.
> 
> Ok for trunk?
> Matthew

OK, but please write a follow-up to fix the pre-existing tests.

Thanks,
James

> 
> gcc/testsuite
> 2015-08-12  Matthew Wahab  
> 
>   * gcc.target/aarch64/atomic-inst-cas.c: New.
>   * gcc.target/aarch64/atomic-inst-ops.inc: New.
> 



Re: [Aarch64][3/3] Add tests for atomic compare-and-swap instructions.

2015-08-12 Thread Matthew Wahab

On 12/08/15 11:51, Andrew Pinski wrote:

On Wed, Aug 12, 2015 at 6:16 PM, Matthew Wahab
 wrote:

ARMv8.1 adds instructions for atomic compare-and-swap with optional
memory ordering specifiers. This patch adds tests for the
compare-and-swap instructions as two files. The first is support code to
run the test with a range of types and memory models, the second is the
test for the CAS instruction.


I noticed you did not change the other cas testcases so they don't set
lse.  This can cause those testcases to fail if a cpu defaults to
having LSE.
I am going to be modifying a cpu to default to LSE enabled soonish.



I'll see what I can do.
Matthew


Re: [Aarch64][3/3] Add tests for atomic compare-and-swap instructions.

2015-08-12 Thread Andrew Pinski
On Wed, Aug 12, 2015 at 6:16 PM, Matthew Wahab
 wrote:
> ARMv8.1 adds instructions for atomic compare-and-swap with optional
> memory ordering specifiers. This patch adds tests for the
> compare-and-swap instructions as two files. The first is support code to
> run the test with a range of types and memory models, the second is the
> test for the CAS instruction.
>
> Tested the series for aarch64-none-linux-gnu with native bootstrap and make
> check and for aarch64-none-elf with cross-compiled check-gcc. Also tested
> aarch64-none-elf with cross-compiled check-gcc on an emulator that supports
> ARMv8.1.
>
> Ok for trunk?


I noticed you did not change the other cas testcases so they don't set
lse.  This can cause those testcases to fail if a cpu defaults to
having LSE.
I am going to be modifying a cpu to default to LSE enabled soonish.

Thanks,
Andrew

> Matthew
>
> gcc/testsuite
> 2015-08-12  Matthew Wahab  
>
> * gcc.target/aarch64/atomic-inst-cas.c: New.
> * gcc.target/aarch64/atomic-inst-ops.inc: New.
>


[Aarch64][3/3] Add tests for atomic compare-and-swap instructions.

2015-08-12 Thread Matthew Wahab

ARMv8.1 adds instructions for atomic compare-and-swap with optional
memory ordering specifiers. This patch adds tests for the
compare-and-swap instructions as two files. The first is support code to
run the test with a range of types and memory models, the second is the
test for the CAS instruction.

Tested the series for aarch64-none-linux-gnu with native bootstrap and make
check and for aarch64-none-elf with cross-compiled check-gcc. Also tested
aarch64-none-elf with cross-compiled check-gcc on an emulator that supports
ARMv8.1.

Ok for trunk?
Matthew

gcc/testsuite
2015-08-12  Matthew Wahab  

* gcc.target/aarch64/atomic-inst-cas.c: New.
* gcc.target/aarch64/atomic-inst-ops.inc: New.

>From c72302f2a0bc4d95a0b933e54332d551295040bf Mon Sep 17 00:00:00 2001
From: Matthew Wahab 
Date: Mon, 3 Aug 2015 18:10:37 +0100
Subject: [PATCH 3/3] Add tests for CAS instruction.

Change-Id: I42a46c2f81f1200a893620ba96323ce785873e8d
---
 gcc/testsuite/gcc.target/aarch64/atomic-inst-cas.c | 61 ++
 .../gcc.target/aarch64/atomic-inst-ops.inc | 53 +++
 2 files changed, 114 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/aarch64/atomic-inst-cas.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/atomic-inst-ops.inc

diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-inst-cas.c b/gcc/testsuite/gcc.target/aarch64/atomic-inst-cas.c
new file mode 100644
index 000..f6f2892
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-inst-cas.c
@@ -0,0 +1,61 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=armv8-a+lse" } */
+
+/* Test ARMv8.1-A CAS instruction.  */
+
+#include "atomic-inst-ops.inc"
+
+#define TEST TEST_TWO
+
+#define CAS_ATOMIC(FN, TY, MODEL1, MODEL2)\
+  int FNNAME (FN, TY) (TY* val, TY* foo, TY* bar)			\
+  {	\
+int model_s = MODEL1;		\
+int model_f = MODEL2;		\
+/* The success memory ordering must be at least as strong as	\
+   the failure memory ordering.  */	\
+if (model_s < model_f)		\
+  return 0;\
+/* Ignore invalid memory orderings.  */\
+if (model_f == __ATOMIC_RELEASE || model_f == __ATOMIC_ACQ_REL)	\
+  return 0;\
+return __atomic_compare_exchange_n (val, foo, bar, 0, model_s, model_f); \
+  }
+
+#define CAS_ATOMIC_NORETURN(FN, TY, MODEL1, MODEL2)			\
+  void FNNAME (FN, TY) (TY* val, TY* foo, TY* bar)			\
+  {	\
+int model_s = MODEL1;		\
+int model_f = MODEL2;		\
+/* The success memory ordering must be at least as strong as	\
+   the failure memory ordering.  */	\
+if (model_s < model_f)		\
+  return;\
+/* Ignore invalid memory orderings.  */\
+if (model_f == __ATOMIC_RELEASE || model_f == __ATOMIC_ACQ_REL)	\
+  return;\
+__atomic_compare_exchange_n (val, foo, bar, 0, model_s, model_f);	\
+  }
+
+TEST (cas_atomic, CAS_ATOMIC)
+TEST (cas_atomic_noreturn, CAS_ATOMIC_NORETURN)
+
+
+/* { dg-final { scan-assembler-times "casb\t" 4} } */
+/* { dg-final { scan-assembler-times "casab\t" 20} } */
+/* { dg-final { scan-assembler-times "caslb\t" 4} } */
+/* { dg-final { scan-assembler-times "casalb\t" 36} } */
+
+/* { dg-final { scan-assembler-times "cash\t" 4} } */
+/* { dg-final { scan-assembler-times "casah\t" 20} } */
+/* { dg-final { scan-assembler-times "caslh\t" 4} } */
+/* { dg-final { scan-assembler-times "casalh\t" 36} } */
+
+/* { dg-final { scan-assembler-times "cas\t" 8} } */
+/* { dg-final { scan-assembler-times "casa\t" 40} } */
+/* { dg-final { scan-assembler-times "casl\t" 8} } */
+/* { dg-final { scan-assembler-times "casal\t" 72} } */
+
+/* { dg-final { scan-assembler-not "ldaxr\t" } } */
+/* { dg-final { scan-assembler-not "stlxr\t" } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-inst-ops.inc b/gcc/testsuite/gcc.target/aarch64/atomic-inst-ops.inc
new file mode 100644
index 000..72c7e5c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-inst-ops.inc
@@ -0,0 +1,53 @@
+/* Support code for atomic instruction tests.  */
+
+/* Define types names without spaces.  */
+typedef unsigned char uchar;
+typedef unsigned short ushort;
+typedef unsigned int uint;
+typedef long long longlong;
+typedef unsigned long long ulonglong;
+typedef __int128_t int128;
+typedef __uint128_t uint128;
+
+#define FNNAME(NAME,TY) NAME
+
+/* Expand one-model functions.  */
+#define TEST_M1(NAME, FN, TY, MODEL, DUMMY)	\
+  FN (test_##NAME##_##TY, TY, MODEL)
+
+/* Expand two-model functions.  */
+#define TEST_M2(NAME, FN, TY, MODEL1, MODEL2)	\
+  FN (test_##NAME##_##TY, TY, MODEL1, MODEL2)
+
+/* Typest to test.  */
+#define TEST_TY(NAME, FN, N, MODEL1, MODEL2)		\
+  TEST_M##N (NAME, FN, char, MODEL1, MODEL2)		\
+  TEST_M##N (NAME, FN, uchar, MODEL1, MODEL2)		\
+  TEST_M##N (NAME, FN, short, MODEL1, MODEL2)		\
+  TEST_M##N (NAME, FN, ushort, MODEL1, MODEL2)		\
+  TEST_M##N (NAME, FN, int, MODEL1, MODE