FW: [Aarch64][BE][2/2] Fix vector load/stores to not use ld1/st1
On 20/11/2014 18:13, Marcus Shawcroft marcus.shawcr...@gmail.com wrote: On 14 November 2014 16:48, Alan Hayward alan.hayw...@arm.com wrote: This is a new version of my BE patch from a few weeks ago. This is part 2 and covers all the aarch64 changes. When combined with the first patch, It fixes up movoi/ci/xi for Big Endian, so that we end up with the lab of a big-endian integer to be in the low byte of the highest-numbered register. This patch requires part 1 and David Sherwood’s patch: [AArch64] [BE] [1/2] Make large opaque integer modes endianness-safe. When tested with David’s patch and [1/2] of this patch, no regressions were seen when testing aarch64 and x86_64 on make check. Changelog: 2014-11-14 Alan Hayward alan.hayw...@arm.com * config/aarch64/aarch64.c (aarch64_classify_address): Allow extra addressing modes for BE. (aarch64_print_operand): new operand for printing a q register+1. Just a bunch of ChangeLog nits. +void aarch64_simd_emit_reg_reg_move (rtx *operands, enum machine_mode mode, + unsigned int count); Drop the formal argument names. Can you respin with these changes please. /Marcus New version. Identical to previous version of the patch except for: * removal of parameter names in aarch64-protos.h * new changelog 2014-11-21 Alan Hayward alan.hayw...@arm.com PR 57233 PR 59810 * config/aarch64/aarch64.c (aarch64_classify_address): Allow extra addressing modes for BE. (aarch64_print_operand): New operand for printing a q register+1. (aarch64_simd_emit_reg_reg_move): Define. (aarch64_simd_disambiguate_copy): Remove. * config/aarch64/aarch64-protos.h (aarch64_simd_emit_reg_reg_move): Define. (aarch64_simd_disambiguate_copy): Remove. * config/aarch64/aarch64-simd.md (define_split): Use aarch64_simd_emit_reg_reg_move. (define_expand movmode): Less restrictive predicates. (define_insn *aarch64_movmode): Simplify and only allow for LE. (define_insn *aarch64_be_movoi): Define. (define_insn *aarch64_be_movci): Define. (define_insn *aarch64_be_movxi): Define. (define_split): OI mov. Use aarch64_simd_emit_reg_reg_move. (define_split): CI mov. Use aarch64_simd_emit_reg_reg_move. (define_split): XI mov. Use aarch64_simd_emit_reg_reg_move. Alan. 0001-BE-fix-load-stores.-Aarch64-code.-v2.patch Description: Binary data
Re: FW: [Aarch64][BE][2/2] Fix vector load/stores to not use ld1/st1
On 21 November 2014 12:11, Alan Hayward alan.hayw...@arm.com wrote: 2014-11-21 Alan Hayward alan.hayw...@arm.com PR 57233 PR 59810 * config/aarch64/aarch64.c (aarch64_classify_address): Allow extra addressing modes for BE. (aarch64_print_operand): New operand for printing a q register+1. (aarch64_simd_emit_reg_reg_move): Define. (aarch64_simd_disambiguate_copy): Remove. * config/aarch64/aarch64-protos.h (aarch64_simd_emit_reg_reg_move): Define. (aarch64_simd_disambiguate_copy): Remove. * config/aarch64/aarch64-simd.md (define_split): Use aarch64_simd_emit_reg_reg_move. (define_expand movmode): Less restrictive predicates. (define_insn *aarch64_movmode): Simplify and only allow for LE. (define_insn *aarch64_be_movoi): Define. (define_insn *aarch64_be_movci): Define. (define_insn *aarch64_be_movxi): Define. (define_split): OI mov. Use aarch64_simd_emit_reg_reg_move. (define_split): CI mov. Use aarch64_simd_emit_reg_reg_move. (define_split): XI mov. Use aarch64_simd_emit_reg_reg_move. I don;t think we should claim to resolve 57233 here. The solution to 57233 from Marc just happened to expose the BE issues in aarch64. Otherwise OK. /Marcus
Re: [Aarch64][BE][2/2] Fix vector load/stores to not use ld1/st1
On 14 November 2014 16:48, Alan Hayward alan.hayw...@arm.com wrote: This is a new version of my BE patch from a few weeks ago. This is part 2 and covers all the aarch64 changes. When combined with the first patch, It fixes up movoi/ci/xi for Big Endian, so that we end up with the lab of a big-endian integer to be in the low byte of the highest-numbered register. This patch requires part 1 and David Sherwood’s patch: [AArch64] [BE] [1/2] Make large opaque integer modes endianness-safe. When tested with David’s patch and [1/2] of this patch, no regressions were seen when testing aarch64 and x86_64 on make check. Changelog: 2014-11-14 Alan Hayward alan.hayw...@arm.com * config/aarch64/aarch64.c (aarch64_classify_address): Allow extra addressing modes for BE. (aarch64_print_operand): new operand for printing a q register+1. Just a bunch of ChangeLog nits. ChangeLog entries are sentences. All of these entries should start with a capital letter. Perhaps this one would be better written as: Add 'R' specifier. (aarch64_simd_emit_reg_reg_move): replacement for Replace with just: (aarch64_simd_emit_reg_reg_move): Remove. * config/aarch64/aarch64-protos.h (aarch64_simd_emit_reg_reg_move): replacement for aarch64_simd_disambiguate_copy. How about: ( aarch64_simd_disambiguate_copy): Define. etc * config/aarch64/aarch64-simd.md (define_split): Use new aarch64_simd_emit_reg_reg_move. (define_expand movmode): less restrictive predicates. (define_insn *aarch64_movmode): Simplify and only allow for LE. (define_insn *aarch64_be_movoi): New. BE only. Plant ldp or stp. Just say: Define. (define_insn *aarch64_be_movci): New. BE only. No instructions. (define_insn *aarch64_be_movxi): New. BE only. No instructions. Likewise. (define_split): OI mov. Use new aarch64_simd_emit_reg_reg_move. (define_split): CI mov. Use new aarch64_simd_emit_reg_reg_move. On BE plant movs for reg to/from mem case. Drop this part. (define_split): XI mov. Use new aarch64_simd_emit_reg_reg_move. On BE plant movs for reg to/from mem case. Likewise. +void aarch64_simd_emit_reg_reg_move (rtx *operands, enum machine_mode mode, + unsigned int count); Drop the formal argument names. Can you respin with these changes please. /Marcus
[Aarch64][BE][2/2] Fix vector load/stores to not use ld1/st1
This is a new version of my BE patch from a few weeks ago. This is part 2 and covers all the aarch64 changes. When combined with the first patch, It fixes up movoi/ci/xi for Big Endian, so that we end up with the lab of a big-endian integer to be in the low byte of the highest-numbered register. This patch requires part 1 and David Sherwood’s patch: [AArch64] [BE] [1/2] Make large opaque integer modes endianness-safe. When tested with David’s patch and [1/2] of this patch, no regressions were seen when testing aarch64 and x86_64 on make check. Changelog: 2014-11-14 Alan Hayward alan.hayw...@arm.com * config/aarch64/aarch64.c (aarch64_classify_address): Allow extra addressing modes for BE. (aarch64_print_operand): new operand for printing a q register+1. (aarch64_simd_emit_reg_reg_move): replacement for aarch64_simd_disambiguate_copy that plants the required mov. * config/aarch64/aarch64-protos.h (aarch64_simd_emit_reg_reg_move): replacement for aarch64_simd_disambiguate_copy. * config/aarch64/aarch64-simd.md (define_split): Use new aarch64_simd_emit_reg_reg_move. (define_expand movmode): less restrictive predicates. (define_insn *aarch64_movmode): Simplify and only allow for LE. (define_insn *aarch64_be_movoi): New. BE only. Plant ldp or stp. (define_insn *aarch64_be_movci): New. BE only. No instructions. (define_insn *aarch64_be_movxi): New. BE only. No instructions. (define_split): OI mov. Use new aarch64_simd_emit_reg_reg_move. (define_split): CI mov. Use new aarch64_simd_emit_reg_reg_move. On BE plant movs for reg to/from mem case. (define_split): XI mov. Use new aarch64_simd_emit_reg_reg_move. On BE plant movs for reg to/from mem case. Alan. 0001-BE-fix-load-stores.-Aarch64-code.patch Description: Binary data
