Re: [PATCH, AArch64] Add falkor pipeline description.

2017-08-07 Thread Richard Earnshaw (lists) 
On 02/08/17 22:54, Jim Wilson wrote:
> This adds a pipeline description for the Qualcomm Falkor core.  This was
> tested with a bootstrap and make check.  There were no regressions.  This
> gives about 0.5% performance gain on SPEC CPU2006 on our internal tree, which
> has a few other patches that aren't in the FSF tree yet.
> 
> OK?
> 

OK.

R.

> Jim
> 
>   gcc/
>   * config/aarch64/aarch64-cores.def (falkor): Use falkor pipeline.
>   (qdf24xx): Likewise.
>   * config/aarch64/aarch64.md: Include falkor.md.
>   * config/aarch64/falkor.md: New.
> ---
>  gcc/config/aarch64/aarch64-cores.def |   4 +-
>  gcc/config/aarch64/aarch64.md|   1 +
>  gcc/config/aarch64/falkor.md | 681 
> +++
>  3 files changed, 684 insertions(+), 2 deletions(-)
>  create mode 100644 gcc/config/aarch64/falkor.md
> 
> diff --git a/gcc/config/aarch64/aarch64-cores.def 
> b/gcc/config/aarch64/aarch64-cores.def
> index b8d0ba6..1089332 100644
> --- a/gcc/config/aarch64/aarch64-cores.def
> +++ b/gcc/config/aarch64/aarch64-cores.def
> @@ -65,8 +65,8 @@ AARCH64_CORE("thunderxt83",   thunderxt83,   thunderx,  8A, 
>  AARCH64_FL_FOR_ARCH
>  AARCH64_CORE("xgene1",  xgene1,xgene1,8A,  AARCH64_FL_FOR_ARCH8, 
> xgene1, 0x50, 0x000, -1)
>  
>  /* Qualcomm ('Q') cores. */
> -AARCH64_CORE("falkor",  falkor,cortexa57, 8A,  AARCH64_FL_FOR_ARCH8 
> | AARCH64_FL_CRC | AARCH64_FL_CRYPTO | AARCH64_FL_RDMA, qdf24xx,   0x51, 
> 0xC00, -1)
> -AARCH64_CORE("qdf24xx", qdf24xx,   cortexa57, 8A,  AARCH64_FL_FOR_ARCH8 
> | AARCH64_FL_CRC | AARCH64_FL_CRYPTO | AARCH64_FL_RDMA, qdf24xx,   0x51, 
> 0xC00, -1)
> +AARCH64_CORE("falkor",  falkor,falkor,8A,  AARCH64_FL_FOR_ARCH8 
> | AARCH64_FL_CRC | AARCH64_FL_CRYPTO | AARCH64_FL_RDMA, qdf24xx,   0x51, 
> 0xC00, -1)
> +AARCH64_CORE("qdf24xx", qdf24xx,   falkor,8A,  AARCH64_FL_FOR_ARCH8 
> | AARCH64_FL_CRC | AARCH64_FL_CRYPTO | AARCH64_FL_RDMA, qdf24xx,   0x51, 
> 0xC00, -1)
>  
>  /* Samsung ('S') cores. */
>  AARCH64_CORE("exynos-m1",   exynosm1,  exynosm1,  8A,  AARCH64_FL_FOR_ARCH8 
> | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, exynosm1,  0x53, 0x001, -1)
> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> index fc79947..51061b2 100644
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -231,6 +231,7 @@
>  (include "../arm/cortex-a53.md")
>  (include "../arm/cortex-a57.md")
>  (include "../arm/exynos-m1.md")
> +(include "falkor.md")
>  (include "thunderx.md")
>  (include "../arm/xgene1.md")
>  (include "thunderx2t99.md")
> diff --git a/gcc/config/aarch64/falkor.md b/gcc/config/aarch64/falkor.md
> new file mode 100644
> index 000..b422ab3
> --- /dev/null
> +++ b/gcc/config/aarch64/falkor.md
> @@ -0,0 +1,681 @@
> +;; Falkor pipeline description
> +;; Copyright (C) 2017 Free Software Foundation, Inc.
> +;;
> +;; This file is part of GCC.
> +;;
> +;; GCC is free software; you can redistribute it and/or modify it
> +;; under the terms of the GNU General Public License as published by
> +;; the Free Software Foundation; either version 3, or (at your option)
> +;; any later version.
> +;;
> +;; GCC is distributed in the hope that it will be useful, but
> +;; WITHOUT ANY WARRANTY; without even the implied warranty of
> +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> +;; General Public License for more details.
> +;;
> +;; You should have received a copy of the GNU General Public License
> +;; along with GCC; see the file COPYING3.  If not see
> +;; .
> +
> +(define_automaton "falkor")
> +
> +;; Complex int instructions (e.g. multiply and divide) execute in the X
> +;; pipeline.  Simple int instructions execute in the X, Y, and Z pipelines.
> +
> +(define_cpu_unit "falkor_x" "falkor")
> +(define_cpu_unit "falkor_y" "falkor")
> +(define_cpu_unit "falkor_z" "falkor")
> +
> +;; Branches execute in the B pipeline or in one of the int pipelines 
> depending
> +;; on how complex it is.  Simple int insns (like movz) can also execute here.
> +
> +(define_cpu_unit "falkor_b" "falkor")
> +
> +;; Vector and FP insns execute in the VX and VY pipelines.
> +
> +(define_automaton "falkor_vfp")
> +
> +(define_cpu_unit "falkor_vx" "falkor_vfp")
> +(define_cpu_unit "falkor_vy" "falkor_vfp")
> +
> +;; Loads execute in the LD pipeline.
> +;; Stores execute in the ST, SD, and VSD pipelines, for address, data, and
> +;; vector data.
> +
> +(define_automaton "falkor_mem")
> +
> +(define_cpu_unit "falkor_ld" "falkor_mem")
> +(define_cpu_unit "falkor_st" "falkor_mem")
> +(define_cpu_unit "falkor_sd" "falkor_mem")
> +(define_cpu_unit "falkor_vsd" "falkor_mem")
> +
> +;; The GTOV and VTOG pipelines are for general to vector reg moves, and vice
> +;; versa.
> +
> +(define_cpu_unit "falkor_gtov" "falkor")
> +(define_cpu_unit "falkor_vtog" "falkor")
> +
> +;; Common reservation combinations.
> +
> +(define_reservation "falkor_vxvy"

[PATCH, AArch64] Add falkor pipeline description.

2017-08-02 Thread Jim Wilson 
This adds a pipeline description for the Qualcomm Falkor core.  This was
tested with a bootstrap and make check.  There were no regressions.  This
gives about 0.5% performance gain on SPEC CPU2006 on our internal tree, which
has a few other patches that aren't in the FSF tree yet.

OK?

Jim

gcc/
* config/aarch64/aarch64-cores.def (falkor): Use falkor pipeline.
(qdf24xx): Likewise.
* config/aarch64/aarch64.md: Include falkor.md.
* config/aarch64/falkor.md: New.
---
 gcc/config/aarch64/aarch64-cores.def |   4 +-
 gcc/config/aarch64/aarch64.md|   1 +
 gcc/config/aarch64/falkor.md | 681 +++
 3 files changed, 684 insertions(+), 2 deletions(-)
 create mode 100644 gcc/config/aarch64/falkor.md

diff --git a/gcc/config/aarch64/aarch64-cores.def 
b/gcc/config/aarch64/aarch64-cores.def
index b8d0ba6..1089332 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -65,8 +65,8 @@ AARCH64_CORE("thunderxt83",   thunderxt83,   thunderx,  8A,  
AARCH64_FL_FOR_ARCH
 AARCH64_CORE("xgene1",  xgene1,xgene1,8A,  AARCH64_FL_FOR_ARCH8, 
xgene1, 0x50, 0x000, -1)
 
 /* Qualcomm ('Q') cores. */
-AARCH64_CORE("falkor",  falkor,cortexa57, 8A,  AARCH64_FL_FOR_ARCH8 | 
AARCH64_FL_CRC | AARCH64_FL_CRYPTO | AARCH64_FL_RDMA, qdf24xx,   0x51, 0xC00, 
-1)
-AARCH64_CORE("qdf24xx", qdf24xx,   cortexa57, 8A,  AARCH64_FL_FOR_ARCH8 | 
AARCH64_FL_CRC | AARCH64_FL_CRYPTO | AARCH64_FL_RDMA, qdf24xx,   0x51, 0xC00, 
-1)
+AARCH64_CORE("falkor",  falkor,falkor,8A,  AARCH64_FL_FOR_ARCH8 | 
AARCH64_FL_CRC | AARCH64_FL_CRYPTO | AARCH64_FL_RDMA, qdf24xx,   0x51, 0xC00, 
-1)
+AARCH64_CORE("qdf24xx", qdf24xx,   falkor,8A,  AARCH64_FL_FOR_ARCH8 | 
AARCH64_FL_CRC | AARCH64_FL_CRYPTO | AARCH64_FL_RDMA, qdf24xx,   0x51, 0xC00, 
-1)
 
 /* Samsung ('S') cores. */
 AARCH64_CORE("exynos-m1",   exynosm1,  exynosm1,  8A,  AARCH64_FL_FOR_ARCH8 | 
AARCH64_FL_CRC | AARCH64_FL_CRYPTO, exynosm1,  0x53, 0x001, -1)
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index fc79947..51061b2 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -231,6 +231,7 @@
 (include "../arm/cortex-a53.md")
 (include "../arm/cortex-a57.md")
 (include "../arm/exynos-m1.md")
+(include "falkor.md")
 (include "thunderx.md")
 (include "../arm/xgene1.md")
 (include "thunderx2t99.md")
diff --git a/gcc/config/aarch64/falkor.md b/gcc/config/aarch64/falkor.md
new file mode 100644
index 000..b422ab3
--- /dev/null
+++ b/gcc/config/aarch64/falkor.md
@@ -0,0 +1,681 @@
+;; Falkor pipeline description
+;; Copyright (C) 2017 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but
+;; WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+;; General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; .
+
+(define_automaton "falkor")
+
+;; Complex int instructions (e.g. multiply and divide) execute in the X
+;; pipeline.  Simple int instructions execute in the X, Y, and Z pipelines.
+
+(define_cpu_unit "falkor_x" "falkor")
+(define_cpu_unit "falkor_y" "falkor")
+(define_cpu_unit "falkor_z" "falkor")
+
+;; Branches execute in the B pipeline or in one of the int pipelines depending
+;; on how complex it is.  Simple int insns (like movz) can also execute here.
+
+(define_cpu_unit "falkor_b" "falkor")
+
+;; Vector and FP insns execute in the VX and VY pipelines.
+
+(define_automaton "falkor_vfp")
+
+(define_cpu_unit "falkor_vx" "falkor_vfp")
+(define_cpu_unit "falkor_vy" "falkor_vfp")
+
+;; Loads execute in the LD pipeline.
+;; Stores execute in the ST, SD, and VSD pipelines, for address, data, and
+;; vector data.
+
+(define_automaton "falkor_mem")
+
+(define_cpu_unit "falkor_ld" "falkor_mem")
+(define_cpu_unit "falkor_st" "falkor_mem")
+(define_cpu_unit "falkor_sd" "falkor_mem")
+(define_cpu_unit "falkor_vsd" "falkor_mem")
+
+;; The GTOV and VTOG pipelines are for general to vector reg moves, and vice
+;; versa.
+
+(define_cpu_unit "falkor_gtov" "falkor")
+(define_cpu_unit "falkor_vtog" "falkor")
+
+;; Common reservation combinations.
+
+(define_reservation "falkor_vxvy" "falkor_vx|falkor_vy")
+(define_reservation "falkor_zb"   "falkor_z|falkor_b")
+(define_reservation "falkor_xyz"  "falkor_x|falkor_y|falkor_z")
+(define_reservation "falkor_xyzb" "falkor_x|falkor_y|falkor_z|falkor_b")
+
+;; SIMD Floating-Point Instructions
+
+(define_insn_reservation