Re: [PATCH, rs6000] Fix vec_mulo and vec_mule instruction generation

2017-06-19 Thread Segher Boessenkool 
Hi Carl,

On Fri, Jun 16, 2017 at 02:19:05PM -0700, Carl Love wrote:
> * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add

Indent is broken on this line.

>   ALTIVEC_BUILTIN_VMULESW, ALTIVEC_BUILTIN_VMULEUW,
>   ALTIVEC_BUILTIN_VMULOSW, ALTIVEC_BUILTIN_VMULOUW enties.

Typo ("entries").

>   * config/rs6000/rs6000.c (rs6000_gimple_fold_builtin(),
>   builtin_function_type()): Add needed ALTIVEC_BUILTIN_* case
>   statements.

No () please, just the names.

>   * config/rs6000/altivec.md (define_c_enum "unspec",
>   define_expand "vec_widen_umult_even_v4si",
>   define_expand "vec_widen_smult_even_v4si",
>   define_expand "vec_widen_umult_odd_v4si",
>   define_expand "vec_widen_smult_odd_v4si",
>   define_insn "altivec_vmuleuw", define_insn "altivec_vmulesw",
>   define_insn "altivec_vmulouw",  define_insn "altivec_vmulosw"): Add
>   support to generate vmuleuw, vmulesw, vmulouw, vmulosw instructions.

(UNSPEC_VMULEUW, UNSPEC_VMULESW, UNSPEC_VMULOUW, UNSPEC_VMULOSW):
New enum "unspec" values.
(vec_widen_umult_even_v4si, vec_widen_smult_even_v4si,
vec_widen_umult_odd_v4si, vec_widen_smult_odd_v4si, altivec_vmuleuw,
altivec_vmulesw, altivec_vmulouw, altivec_vmulosw): New patterns.

(Or similar.  Mention all new names added.  Usually for new things, just
saying "New." or "New frobnitz." is enough; the changelog does not describe
the design, or why you added something: it says just what changed).

> +(define_expand "vec_widen_umult_even_v4si"
> +  [(use (match_operand:V2DI 0 "register_operand" ""))
> +   (use (match_operand:V4SI 1 "register_operand" ""))
> +   (use (match_operand:V4SI 2 "register_operand" ""))]

You can leave off the default (empty) constraint strings, in expanders.

> +  "TARGET_ALTIVEC"
> +{
> +  if (VECTOR_ELT_ORDER_BIG)
> +emit_insn (gen_altivec_vmuleuw (operands[0], operands[1],
> operands[2]));

Your patch was wrapped in the mail.  Please try to prevent that, so that
other people can apply the patch to test out, etc.

> +(define_insn "altivec_vmuleuw"
> +  [(set (match_operand:V2DI 0 "register_operand" "=v")
> +(unspec:V2DI [(match_operand:V4SI 1 "register_operand" "v")
> +  (match_operand:V4SI 2 "register_operand" "v")]
> +  UNSPEC_VMULEUW))]

The one-but-last line should be indented with tabs instead of spaces, too.
(This happens a few time more later in the patch; please check it all).

Okay for trunk with those last nits fixed.  Thanks!


Segher

[PATCH, rs6000] Fix vec_mulo and vec_mule instruction generation

2017-06-16 Thread Carl Love 
GCC Maintainers:

The support for the vec_mulo and vec_mule has yet another bug.  For the
case of signed/unsigned integer arguments the builtin generates the half
word instruction not the word instruction.  This patch fixes the issue.
The fix  has been tested and verified on powerpc64le-unknown-linux-gnu
(Power 8 LE)

Is the patch OK for gcc mainline?

  Carl Love


-
>From 3127a3f9c8480fde428c4a13bc37d6eaefd0edfe Mon Sep 17 00:00:00 2001
From: Carl Love 
Date: Fri, 16 Jun 2017 16:10:56 -0500
Subject: [PATCH] vec_mule, vec_mulo fix 2

gcc/ChangeLog:

2017-06-17  Carl Love  

* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
ALTIVEC_BUILTIN_VMULESW, ALTIVEC_BUILTIN_VMULEUW,
ALTIVEC_BUILTIN_VMULOSW, ALTIVEC_BUILTIN_VMULOUW enties.
* config/rs6000/rs6000.c (rs6000_gimple_fold_builtin(),
builtin_function_type()): Add needed ALTIVEC_BUILTIN_* case
statements.
* config/rs6000/altivec.md (define_c_enum "unspec",
define_expand "vec_widen_umult_even_v4si",
define_expand "vec_widen_smult_even_v4si",
define_expand "vec_widen_umult_odd_v4si",
define_expand "vec_widen_smult_odd_v4si",
define_insn "altivec_vmuleuw", define_insn "altivec_vmulesw",
define_insn "altivec_vmulouw",  define_insn "altivec_vmulosw"): Add
support to generate vmuleuw, vmulesw, vmulouw, vmulosw instructions.
* config/rs6000/rs6000-builtin.def (VMLEUW, VMULESW, VMULOUW,
VMULOSW): Add definitions.
---
 gcc/config/rs6000/altivec.md | 91

 gcc/config/rs6000/rs6000-builtin.def |  8 
 gcc/config/rs6000/rs6000-c.c | 12 +++--
 gcc/config/rs6000/rs6000.c   |  6 +++
 4 files changed, 113 insertions(+), 4 deletions(-)

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 487b9a4..142300a 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -36,10 +36,14 @@
UNSPEC_VMULESB
UNSPEC_VMULEUH
UNSPEC_VMULESH
+   UNSPEC_VMULEUW
+   UNSPEC_VMULESW
UNSPEC_VMULOUB
UNSPEC_VMULOSB
UNSPEC_VMULOUH
UNSPEC_VMULOSH
+   UNSPEC_VMULOUW
+   UNSPEC_VMULOSW
UNSPEC_VPKPX
UNSPEC_VPACK_SIGN_SIGN_SAT
UNSPEC_VPACK_SIGN_UNS_SAT
@@ -1412,6 +1416,32 @@
   DONE;
 })
 
+(define_expand "vec_widen_umult_even_v4si"
+  [(use (match_operand:V2DI 0 "register_operand" ""))
+   (use (match_operand:V4SI 1 "register_operand" ""))
+   (use (match_operand:V4SI 2 "register_operand" ""))]
+  "TARGET_ALTIVEC"
+{
+  if (VECTOR_ELT_ORDER_BIG)
+emit_insn (gen_altivec_vmuleuw (operands[0], operands[1],
operands[2]));
+  else
+emit_insn (gen_altivec_vmulouw (operands[0], operands[1],
operands[2]));
+  DONE;
+})
+
+(define_expand "vec_widen_smult_even_v4si"
+  [(use (match_operand:V2DI 0 "register_operand" ""))
+   (use (match_operand:V4SI 1 "register_operand" ""))
+   (use (match_operand:V4SI 2 "register_operand" ""))]
+  "TARGET_ALTIVEC"
+{
+  if (VECTOR_ELT_ORDER_BIG)
+emit_insn (gen_altivec_vmulesw (operands[0], operands[1],
operands[2]));
+  else
+emit_insn (gen_altivec_vmulosw (operands[0], operands[1],
operands[2]));
+  DONE;
+})
+
 (define_expand "vec_widen_umult_odd_v16qi"
   [(use (match_operand:V8HI 0 "register_operand" ""))
(use (match_operand:V16QI 1 "register_operand" ""))
@@ -1464,6 +1494,32 @@
   DONE;
 })
 
+(define_expand "vec_widen_umult_odd_v4si"
+  [(use (match_operand:V2DI 0 "register_operand" ""))
+   (use (match_operand:V4SI 1 "register_operand" ""))
+   (use (match_operand:V4SI 2 "register_operand" ""))]
+  "TARGET_ALTIVEC"
+{
+  if (VECTOR_ELT_ORDER_BIG)
+emit_insn (gen_altivec_vmulouw (operands[0], operands[1],
operands[2]));
+  else
+emit_insn (gen_altivec_vmuleuw (operands[0], operands[1],
operands[2]));
+  DONE;
+})
+
+(define_expand "vec_widen_smult_odd_v4si"
+  [(use (match_operand:V2DI 0 "register_operand" ""))
+   (use (match_operand:V4SI 1 "register_operand" ""))
+   (use (match_operand:V4SI 2 "register_operand" ""))]
+  "TARGET_ALTIVEC"
+{
+  if (VECTOR_ELT_ORDER_BIG)
+emit_insn (gen_altivec_vmulosw (operands[0], operands[1],
operands[2]));
+  else
+emit_insn (gen_altivec_vmulesw (operands[0], operands[1],
operands[2]));
+  DONE;
+})
+
 (define_insn "altivec_vmuleub"
   [(set (match_operand:V8HI 0 "register_operand" "=v")
 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
@@ -1536,6 +1592,41 @@
   "vmulosh %0,%1,%2"
   [(set_attr "type" "veccomplex")])
 
+(define_insn "altivec_vmuleuw"
+  [(set (match_operand:V2DI 0 "register_operand" "=v")
+(unspec:V2DI [(match_operand:V4SI 1 "register_operand" "v")
+  (match_operand:V4SI 2 "register_operand" "v")]
+UNSPEC_VMULEUW))]
+  "TARGET_ALTIVEC"
+  "vmuleuw %0,%1,%2"
+  [(set_attr "type" "veccomplex")])
+
+(define_insn "altivec_vmulouw"
+  [(set