Re: [PATCH, rs6000] Add support for int versions of vec_adde

[Andreas Schwab]

Bill Seurer  writes:

> * gcc.target/powerpc/vec-adde.c: New test.
> * gcc.target/powerpc/vec-adde-int128.c: New test.

-m32:

FAIL: gcc.target/powerpc/vec-adde.c execution test
FAIL: gcc.target/powerpc/vec-adde-int128.c (test for excess errors)
Excess errors:
/daten/gcc/gcc-20160501/gcc/testsuite/gcc.target/powerpc/vec-adde-int128.c:66:30:
 error: '__int128' is not supported on this target

Andreas.

-- 
Andreas Schwab, sch...@linux-m68k.org
GPG Key fingerprint = 58CA 54C7 6D53 942B 1756  01D3 44D5 214B 8276 4ED5
"And now for something completely different."

Re: [PATCH, rs6000] Add support for int versions of vec_adde

[David Edelsohn]

On Wed, Apr 13, 2016 at 10:47 AM, Bill Seurer  wrote:
> Here is an updated patch:
>
>
> This patch adds support for the signed and unsigned int versions of the
> vec_adde altivec builtins from the Power Architecture 64-Bit ELF V2 ABI
> OpenPOWER ABI for Linux Supplement (16 July 2015 Version 1.1). There are
> many of the builtins that are missing and this is the first of a series
> of patches to add them.
>
> There aren't instructions for the int versions of vec_adde so the
> output code is built from other built-ins that do have instructions
> which in this case is just two vec_adds.
>
> The new test cases are executable tests which verify that the generated
> code produces expected values. C macros were used so that the same
> test case could be used for both the signed and unsigned versions. An
> extra executable test case is also included to ensure that the modified
> support for the __int128 versions of vec_adde is not broken. The same
> test case could not be used for both int and __int128 because of some
> differences in loading and storing the vectors.
>
> Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no
> regressions. Is this ok for trunk?
>
> [gcc]
>
> 2016-04-06 Bill Seurer 
>
> * config/rs6000/rs6000-builtin.def (vec_adde): Change vec_adde to a
> special case builtin.
> * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Remove
> ALTIVEC_BUILTIN_VEC_ADDE.
> * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Add
> support for ALTIVEC_BUILTIN_VEC_ADDE.
> * config/rs6000/rs6000.c (altivec_init_builtins): Add definition
> for __builtin_vec_adde.
>
> [gcc/testsuite]
>
> 2016-04-06 Bill Seurer 
>
> * gcc.target/powerpc/vec-adde.c: New test.
> * gcc.target/powerpc/vec-adde-int128.c: New test.

The revised patch is okay for GCC 7, with the changes requested by Segher.

Thanks, David

Re: [PATCH, rs6000] Add support for int versions of vec_adde

[Bill Seurer]

Segher pointed out a few formatting issues via IRC which I have fixed.

On 04/13/16 09:47, Bill Seurer wrote:

Here is an updated patch:


This patch adds support for the signed and unsigned int versions of the
vec_adde altivec builtins from the Power Architecture 64-Bit ELF V2 ABI
OpenPOWER ABI for Linux Supplement (16 July 2015 Version 1.1). There are
many of the builtins that are missing and this is the first of a series
of patches to add them.

There aren't instructions for the int versions of vec_adde so the
output code is built from other built-ins that do have instructions
which in this case is just two vec_adds.

The new test cases are executable tests which verify that the generated
code produces expected values. C macros were used so that the same
test case could be used for both the signed and unsigned versions. An
extra executable test case is also included to ensure that the modified
support for the __int128 versions of vec_adde is not broken. The same
test case could not be used for both int and __int128 because of some
differences in loading and storing the vectors.

Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no
regressions. Is this ok for trunk?

[gcc]

2016-04-06 Bill Seurer 

* config/rs6000/rs6000-builtin.def (vec_adde): Change vec_adde to a
special case builtin.
* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Remove
ALTIVEC_BUILTIN_VEC_ADDE.
* config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Add
support for ALTIVEC_BUILTIN_VEC_ADDE.
* config/rs6000/rs6000.c (altivec_init_builtins): Add definition
for __builtin_vec_adde.

[gcc/testsuite]

2016-04-06 Bill Seurer 

* gcc.target/powerpc/vec-adde.c: New test.
* gcc.target/powerpc/vec-adde-int128.c: New test.


Index: gcc/config/rs6000/rs6000-builtin.def
===
--- gcc/config/rs6000/rs6000-builtin.def(revision 234936)
+++ gcc/config/rs6000/rs6000-builtin.def(working copy)
@@ -951,7 +951,6 @@ BU_ALTIVEC_X (VEC_EXT_V4SF, "vec_ext_v4sf", CO
 before we get to the point about classifying the builtin type.  */

  /* 3 argument Altivec overloaded builtins.  */
-BU_ALTIVEC_OVERLOAD_3 (ADDE,  "adde")
  BU_ALTIVEC_OVERLOAD_3 (ADDEC,"addec")
  BU_ALTIVEC_OVERLOAD_3 (MADD,   "madd")
  BU_ALTIVEC_OVERLOAD_3 (MADDS,  "madds")
@@ -1137,6 +1136,7 @@ BU_ALTIVEC_OVERLOAD_P (VCMPGT_P,   "vcmpgt_p")
  BU_ALTIVEC_OVERLOAD_P (VCMPGE_P,   "vcmpge_p")

  /* Overloaded Altivec builtins that are handled as special cases.  */
+BU_ALTIVEC_OVERLOAD_X (ADDE,  "adde")
  BU_ALTIVEC_OVERLOAD_X (CTF,  "ctf")
  BU_ALTIVEC_OVERLOAD_X (CTS,  "cts")
  BU_ALTIVEC_OVERLOAD_X (CTU,  "ctu")
Index: gcc/config/rs6000/rs6000-c.c
===
--- gcc/config/rs6000/rs6000-c.c(revision 234936)
+++ gcc/config/rs6000/rs6000-c.c(working copy)
@@ -842,11 +842,6 @@ const struct altivec_builtin_types altivec_overloa
  RS6000_BTI_unsigned_V1TI, 0 },
{ ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ,
  RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
-  { ALTIVEC_BUILTIN_VEC_ADDE, P8V_BUILTIN_VADDEUQM,
-RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
-RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
-  { ALTIVEC_BUILTIN_VEC_ADDE, P8V_BUILTIN_VADDEUQM,
-RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
{ ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ,
  RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
  RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
@@ -4515,6 +4510,62 @@ assignment for unaligned loads and stores");
  warning (OPT_Wdeprecated, "vec_lvsr is deprecated for little endian; use \
  assignment for unaligned loads and stores");

+  if (fcode == ALTIVEC_BUILTIN_VEC_ADDE)
+{
+  /* vec_adde needs to be special cased because there is no instruction
+ for the {un}signed int version.  */
+  if (nargs != 3)
+   {
+ error ("vec_adde only accepts 3 arguments");
+ return error_mark_node;
+   }
+
+  tree arg0 = (*arglist)[0];
+  tree arg0_type = TREE_TYPE (arg0);
+  tree arg1 = (*arglist)[1];
+  tree arg1_type = TREE_TYPE (arg1);
+  tree arg2 = (*arglist)[2];
+  tree arg2_type = TREE_TYPE (arg2);
+
+  /* All 3 arguments must be vectors of (signed or unsigned) (int or
+ __int128) and the types must match.  */
+  if ((arg0_type != arg1_type) || (arg1_type != arg2_type))
+   goto bad;
+  if (TREE_CODE (arg0_type) != VECTOR_TYPE)
+   goto bad;
+
+  switch (TYPE_MODE (TREE_TYPE (arg0_type)))
+   {
+ /* For {un}signed ints,
+vec_adde (va, vb, carryv) == vec_add (vec_add (va, vb), vec_and 
(carryv, 0x1)).  */
+ case SImode:
+   {
+ vec *params = make_tree_vector();
+ 

Re: [PATCH, rs6000] Add support for int versions of vec_adde

[Bill Seurer]

Here is an updated patch:


This patch adds support for the signed and unsigned int versions of the
vec_adde altivec builtins from the Power Architecture 64-Bit ELF V2 ABI
OpenPOWER ABI for Linux Supplement (16 July 2015 Version 1.1). There are
many of the builtins that are missing and this is the first of a series
of patches to add them.

There aren't instructions for the int versions of vec_adde so the
output code is built from other built-ins that do have instructions
which in this case is just two vec_adds.

The new test cases are executable tests which verify that the generated
code produces expected values. C macros were used so that the same
test case could be used for both the signed and unsigned versions. An
extra executable test case is also included to ensure that the modified
support for the __int128 versions of vec_adde is not broken. The same
test case could not be used for both int and __int128 because of some
differences in loading and storing the vectors.

Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no
regressions. Is this ok for trunk?

[gcc]

2016-04-06 Bill Seurer 

* config/rs6000/rs6000-builtin.def (vec_adde): Change vec_adde to a
special case builtin.
* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Remove
ALTIVEC_BUILTIN_VEC_ADDE.
* config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Add
support for ALTIVEC_BUILTIN_VEC_ADDE.
* config/rs6000/rs6000.c (altivec_init_builtins): Add definition
for __builtin_vec_adde.

[gcc/testsuite]

2016-04-06 Bill Seurer 

* gcc.target/powerpc/vec-adde.c: New test.
* gcc.target/powerpc/vec-adde-int128.c: New test.


Index: gcc/config/rs6000/rs6000-builtin.def
===
--- gcc/config/rs6000/rs6000-builtin.def(revision 234936)
+++ gcc/config/rs6000/rs6000-builtin.def(working copy)
@@ -951,7 +951,6 @@ BU_ALTIVEC_X (VEC_EXT_V4SF, "vec_ext_v4sf", CO
before we get to the point about classifying the builtin type.  */
 
 /* 3 argument Altivec overloaded builtins.  */
-BU_ALTIVEC_OVERLOAD_3 (ADDE,  "adde")
 BU_ALTIVEC_OVERLOAD_3 (ADDEC, "addec")
 BU_ALTIVEC_OVERLOAD_3 (MADD,   "madd")
 BU_ALTIVEC_OVERLOAD_3 (MADDS,  "madds")
@@ -1137,6 +1136,7 @@ BU_ALTIVEC_OVERLOAD_P (VCMPGT_P,   "vcmpgt_p")
 BU_ALTIVEC_OVERLOAD_P (VCMPGE_P,   "vcmpge_p")
 
 /* Overloaded Altivec builtins that are handled as special cases.  */
+BU_ALTIVEC_OVERLOAD_X (ADDE,  "adde")
 BU_ALTIVEC_OVERLOAD_X (CTF,   "ctf")
 BU_ALTIVEC_OVERLOAD_X (CTS,   "cts")
 BU_ALTIVEC_OVERLOAD_X (CTU,   "ctu")
Index: gcc/config/rs6000/rs6000-c.c
===
--- gcc/config/rs6000/rs6000-c.c(revision 234936)
+++ gcc/config/rs6000/rs6000-c.c(working copy)
@@ -842,11 +842,6 @@ const struct altivec_builtin_types altivec_overloa
 RS6000_BTI_unsigned_V1TI, 0 },
   { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ,
 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
-  { ALTIVEC_BUILTIN_VEC_ADDE, P8V_BUILTIN_VADDEUQM,
-RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
-RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
-  { ALTIVEC_BUILTIN_VEC_ADDE, P8V_BUILTIN_VADDEUQM,
-RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
   { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ,
 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
@@ -4515,6 +4510,62 @@ assignment for unaligned loads and stores");
 warning (OPT_Wdeprecated, "vec_lvsr is deprecated for little endian; use \
 assignment for unaligned loads and stores");
 
+  if (fcode == ALTIVEC_BUILTIN_VEC_ADDE)
+{
+  /* vec_adde needs to be special cased because there is no instruction
+ for the {un}signed int version.  */
+  if (nargs != 3)
+   {
+ error ("vec_adde only accepts 3 arguments");
+ return error_mark_node;
+   }
+
+  tree arg0 = (*arglist)[0];
+  tree arg0_type = TREE_TYPE (arg0);
+  tree arg1 = (*arglist)[1];
+  tree arg1_type = TREE_TYPE (arg1);
+  tree arg2 = (*arglist)[2];
+  tree arg2_type = TREE_TYPE (arg2);
+
+  /* All 3 arguments must be vectors of (signed or unsigned) (int or
+ __int128) and the types must match.  */
+  if ((arg0_type != arg1_type) || (arg1_type != arg2_type))
+   goto bad; 
+  if (TREE_CODE (arg0_type) != VECTOR_TYPE)
+   goto bad; 
+
+  switch (TYPE_MODE (TREE_TYPE (arg0_type)))
+   {
+ /* For {un}signed ints, 
+vec_adde (va, vb, carryv) == vec_add (vec_add (va, vb), vec_and 
(carryv, 0x1)).  */
+ case SImode:
+   {
+ vec *params = make_tree_vector();
+ vec_safe_push (params, arg0);
+ vec_safe_push (params, arg1);
+ tree call = 

Re: [PATCH, rs6000] Add support for int versions of vec_adde

[Bill Seurer]

On 04/08/16 09:50, Segher Boessenkool wrote:

Hi Bill,

On Thu, Apr 07, 2016 at 04:04:30PM -0500, Bill Seurer wrote:

On 04/05/16 21:27, David Edelsohn wrote:

On Tue, Apr 5, 2016 at 3:36 PM, Bill Seurer 

 * config/rs6000/rs6000-c.c (altivec_overloaded_builtins,
 altivec_resolve_overloaded_builtin): Remove
 ALTIVEC_BUILTIN_VEC_ADDE
 from altivec_overloaded_builtins structure.  Add support for it
 to
 altivec_resolve_overloaded_builtin function.


A total nit, but...  If you change one thing in one places, and another
in another, put them in the changelog separately.


OK.


+ /* for {un}signed ints,
+vec_adde (va, vb, carryv) == vec_add (vec_add (va, vb),
carryv) */


Same.


Also sentences start with a capital letter.

What is the definition of the builtin?  The machine insn does
va + vb + (carryv & 1); your implementation skips the AND.


From the ABI document:
Purpose:
Returns a vector containing the result of adding each set of the 
corresponding elements of ARG1 and ARG2 with a carry (that has a value 
of either 0 or 1) specified as the ARG3 vector.

Result value:
The value of each element of the result is produced by adding the 
corresponding elements of ARG1 and ARG2 and a carry specified in ARG3 (1 
if there is a carry, 0 otherwise).



It's not really clear what should be done if the carry is not 1 or 0 
from that description because it specifies that the carry IS 1 or 0.


I tried it and the instruction (for __int128's only) does indeed do the 
and which means it will add a 0 if the "carry" is something like 2.  I 
will change the test case to include "bad" values.


I can add an and easily enough.


--- gcc/testsuite/gcc.target/powerpc/vec-adde-int128.c  (revision 0)
+++ gcc/testsuite/gcc.target/powerpc/vec-adde-int128.c  (working copy)
@@ -0,0 +1,78 @@
+/* { dg-do run { target { powerpc64le-*-* } } } */


Will powerpc64 (i.e. BE) not work?


No, it does work.  The other test cases I was using as models only 
targeted LE (though on inspection most if not all of them would also 
work on BE).  I suppose there's no reason to do that here, though.

--

-Bill Seurer

Re: [PATCH, rs6000] Add support for int versions of vec_adde

[Segher Boessenkool]

Hi Bill,

On Thu, Apr 07, 2016 at 04:04:30PM -0500, Bill Seurer wrote:
> On 04/05/16 21:27, David Edelsohn wrote:
> >On Tue, Apr 5, 2016 at 3:36 PM, Bill Seurer  
> >> * config/rs6000/rs6000-c.c (altivec_overloaded_builtins,
> >> altivec_resolve_overloaded_builtin): Remove 
> >> ALTIVEC_BUILTIN_VEC_ADDE
> >> from altivec_overloaded_builtins structure.  Add support for it 
> >> to
> >> altivec_resolve_overloaded_builtin function.

A total nit, but...  If you change one thing in one places, and another
in another, put them in the changelog separately.

> >>+ /* for {un}signed ints,
> >>+vec_adde (va, vb, carryv) == vec_add (vec_add (va, vb), 
> >>carryv) */
> >
> >Same.

Also sentences start with a capital letter.

What is the definition of the builtin?  The machine insn does
va + vb + (carryv & 1); your implementation skips the AND.

> >>--- gcc/testsuite/gcc.target/powerpc/vec-adde-int128.c  (revision 0)
> >>+++ gcc/testsuite/gcc.target/powerpc/vec-adde-int128.c  (working copy)
> >>@@ -0,0 +1,78 @@
> >>+/* { dg-do run { target { powerpc64le-*-* } } } */

Will powerpc64 (i.e. BE) not work?


Segher

Re: [PATCH, rs6000] Add support for int versions of vec_adde

[Bill Seurer]

On 04/05/16 21:27, David Edelsohn wrote:

On Tue, Apr 5, 2016 at 3:36 PM, Bill Seurer  wrote:

This patch adds support for the signed and unsigned int versions of the
vec_adde altivec builtins from the Power Architecture 64-Bit ELF V2 ABI
OpenPOWER ABI for Linux Supplement (16 July 2015 Version 1.1).  There are
many of the builtins that are missing and this is the first of a series
of patches to add them.

There aren't instructions for the int versions of vec_adde so the
output code is built from other built-ins that do have instructions
which in this case is just two vec_adds.

The new test cases are executable tests which verify that the generated
code produces expected values.  C macros were used so that the same
test case could be used for both the signed and unsigned versions.  An
extra executable test case is also included to ensure that the modified
support for the __int128 versions of vec_adde is not broken.  The same
test case could not be used for both int and __int128 because of some
differences in loading and storing the vectors.

Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no
regressions.  Is this ok for trunk?

[gcc]

2016-04-06  Bill Seurer  

 * config/rs6000/rs6000-builtin.def (vec_adde): Change vec_adde to a
 special case builtin.
 * config/rs6000/rs6000-c.c (altivec_overloaded_builtins,
 altivec_resolve_overloaded_builtin): Remove ALTIVEC_BUILTIN_VEC_ADDE
 from altivec_overloaded_builtins structure.  Add support for it to
 altivec_resolve_overloaded_builtin function.
 * config/rs6000/rs6000.c (altivec_init_builtins): Add definition
 for __builtin_vec_adde.

[gcc/testsuite]

2016-04-06  Bill Seurer  

 * gcc.target/powerpc/vec-adde.c: New test.
 * gcc.target/powerpc/vec-adde-int128.c: New test.

Index: gcc/config/rs6000/rs6000-builtin.def
===
--- gcc/config/rs6000/rs6000-builtin.def(revision 234745)
+++ gcc/config/rs6000/rs6000-builtin.def(working copy)
@@ -951,7 +951,6 @@ BU_ALTIVEC_X (VEC_EXT_V4SF, "vec_ext_v4sf", CO
 before we get to the point about classifying the builtin type.  */

  /* 3 argument Altivec overloaded builtins.  */
-BU_ALTIVEC_OVERLOAD_3 (ADDE,  "adde")
  BU_ALTIVEC_OVERLOAD_3 (ADDEC, "addec")
  BU_ALTIVEC_OVERLOAD_3 (MADD,   "madd")
  BU_ALTIVEC_OVERLOAD_3 (MADDS,  "madds")
@@ -1137,6 +1136,7 @@ BU_ALTIVEC_OVERLOAD_P (VCMPGT_P,   "vcmpgt_p")
  BU_ALTIVEC_OVERLOAD_P (VCMPGE_P,   "vcmpge_p")

  /* Overloaded Altivec builtins that are handled as special cases.  */
+BU_ALTIVEC_OVERLOAD_X (ADDE,  "adde")
  BU_ALTIVEC_OVERLOAD_X (CTF,   "ctf")
  BU_ALTIVEC_OVERLOAD_X (CTS,   "cts")
  BU_ALTIVEC_OVERLOAD_X (CTU,   "ctu")
Index: gcc/config/rs6000/rs6000-c.c
===
--- gcc/config/rs6000/rs6000-c.c(revision 234745)
+++ gcc/config/rs6000/rs6000-c.c(working copy)
@@ -842,11 +842,6 @@ const struct altivec_builtin_types altivec_overloa
  RS6000_BTI_unsigned_V1TI, 0 },
{ ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ,
  RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
-  { ALTIVEC_BUILTIN_VEC_ADDE, P8V_BUILTIN_VADDEUQM,
-RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
-RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
-  { ALTIVEC_BUILTIN_VEC_ADDE, P8V_BUILTIN_VADDEUQM,
-RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
{ ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ,
  RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
  RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
@@ -4515,6 +4510,59 @@ assignment for unaligned loads and stores");
  warning (OPT_Wdeprecated, "vec_lvsr is deprecated for little endian; use \
  assignment for unaligned loads and stores");

+  if (fcode == ALTIVEC_BUILTIN_VEC_ADDE)
+{
+  /* vec_adde needs to be special cased because there is no instruction
+ for the {un}signed int version */


End comment sentence with period and two spaces


+  if (nargs != 3)
+   {
+ error ("vec_adde only accepts 3 arguments");
+ return error_mark_node;
+   }
+
+  tree arg0 = (*arglist)[0];
+  tree arg0_type = TREE_TYPE (arg0);
+  tree arg1 = (*arglist)[1];
+  tree arg1_type = TREE_TYPE (arg1);
+  tree arg2 = (*arglist)[2];
+  tree arg2_type = TREE_TYPE (arg2);
+
+  /* All 3 arguments must be vectors of (signed or unsigned) (int or
+ __int128) and the types must match */


Same.


+  if ((arg0_type != arg1_type) || (arg1_type != arg2_type))
+   goto bad;
+  if (TREE_CODE (arg0_type) != VECTOR_TYPE)
+   goto bad;
+
+  switch (TYPE_MODE (TREE_TYPE (arg0_type)))
+   {
+ /* for {un}signed ints,
+vec_adde (va, 

Re: [PATCH, rs6000] Add support for int versions of vec_adde

[David Edelsohn]

On Tue, Apr 5, 2016 at 3:36 PM, Bill Seurer  wrote:
> This patch adds support for the signed and unsigned int versions of the
> vec_adde altivec builtins from the Power Architecture 64-Bit ELF V2 ABI
> OpenPOWER ABI for Linux Supplement (16 July 2015 Version 1.1).  There are
> many of the builtins that are missing and this is the first of a series
> of patches to add them.
>
> There aren't instructions for the int versions of vec_adde so the
> output code is built from other built-ins that do have instructions
> which in this case is just two vec_adds.
>
> The new test cases are executable tests which verify that the generated
> code produces expected values.  C macros were used so that the same
> test case could be used for both the signed and unsigned versions.  An
> extra executable test case is also included to ensure that the modified
> support for the __int128 versions of vec_adde is not broken.  The same
> test case could not be used for both int and __int128 because of some
> differences in loading and storing the vectors.
>
> Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no
> regressions.  Is this ok for trunk?
>
> [gcc]
>
> 2016-04-06  Bill Seurer  
>
> * config/rs6000/rs6000-builtin.def (vec_adde): Change vec_adde to a
> special case builtin.
> * config/rs6000/rs6000-c.c (altivec_overloaded_builtins,
> altivec_resolve_overloaded_builtin): Remove ALTIVEC_BUILTIN_VEC_ADDE
> from altivec_overloaded_builtins structure.  Add support for it to
> altivec_resolve_overloaded_builtin function.
> * config/rs6000/rs6000.c (altivec_init_builtins): Add definition
> for __builtin_vec_adde.
>
> [gcc/testsuite]
>
> 2016-04-06  Bill Seurer  
>
> * gcc.target/powerpc/vec-adde.c: New test.
> * gcc.target/powerpc/vec-adde-int128.c: New test.
>
> Index: gcc/config/rs6000/rs6000-builtin.def
> ===
> --- gcc/config/rs6000/rs6000-builtin.def(revision 234745)
> +++ gcc/config/rs6000/rs6000-builtin.def(working copy)
> @@ -951,7 +951,6 @@ BU_ALTIVEC_X (VEC_EXT_V4SF, "vec_ext_v4sf", CO
> before we get to the point about classifying the builtin type.  */
>
>  /* 3 argument Altivec overloaded builtins.  */
> -BU_ALTIVEC_OVERLOAD_3 (ADDE,  "adde")
>  BU_ALTIVEC_OVERLOAD_3 (ADDEC, "addec")
>  BU_ALTIVEC_OVERLOAD_3 (MADD,   "madd")
>  BU_ALTIVEC_OVERLOAD_3 (MADDS,  "madds")
> @@ -1137,6 +1136,7 @@ BU_ALTIVEC_OVERLOAD_P (VCMPGT_P,   "vcmpgt_p")
>  BU_ALTIVEC_OVERLOAD_P (VCMPGE_P,   "vcmpge_p")
>
>  /* Overloaded Altivec builtins that are handled as special cases.  */
> +BU_ALTIVEC_OVERLOAD_X (ADDE,  "adde")
>  BU_ALTIVEC_OVERLOAD_X (CTF,   "ctf")
>  BU_ALTIVEC_OVERLOAD_X (CTS,   "cts")
>  BU_ALTIVEC_OVERLOAD_X (CTU,   "ctu")
> Index: gcc/config/rs6000/rs6000-c.c
> ===
> --- gcc/config/rs6000/rs6000-c.c(revision 234745)
> +++ gcc/config/rs6000/rs6000-c.c(working copy)
> @@ -842,11 +842,6 @@ const struct altivec_builtin_types altivec_overloa
>  RS6000_BTI_unsigned_V1TI, 0 },
>{ ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ,
>  RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
> -  { ALTIVEC_BUILTIN_VEC_ADDE, P8V_BUILTIN_VADDEUQM,
> -RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
> -RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
> -  { ALTIVEC_BUILTIN_VEC_ADDE, P8V_BUILTIN_VADDEUQM,
> -RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
>{ ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ,
>  RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
>  RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
> @@ -4515,6 +4510,59 @@ assignment for unaligned loads and stores");
>  warning (OPT_Wdeprecated, "vec_lvsr is deprecated for little endian; use 
> \
>  assignment for unaligned loads and stores");
>
> +  if (fcode == ALTIVEC_BUILTIN_VEC_ADDE)
> +{
> +  /* vec_adde needs to be special cased because there is no instruction
> + for the {un}signed int version */

End comment sentence with period and two spaces

> +  if (nargs != 3)
> +   {
> + error ("vec_adde only accepts 3 arguments");
> + return error_mark_node;
> +   }
> +
> +  tree arg0 = (*arglist)[0];
> +  tree arg0_type = TREE_TYPE (arg0);
> +  tree arg1 = (*arglist)[1];
> +  tree arg1_type = TREE_TYPE (arg1);
> +  tree arg2 = (*arglist)[2];
> +  tree arg2_type = TREE_TYPE (arg2);
> +
> +  /* All 3 arguments must be vectors of (signed or unsigned) (int or
> + __int128) and the types must match */

Same.

> +  if ((arg0_type != arg1_type) || (arg1_type != arg2_type))
> +   goto bad;
> +  if (TREE_CODE (arg0_type) != VECTOR_TYPE)
> +   goto bad;
>