Hi,
The Power ISA 2.07 enables some additional forms of existing vector
builtins, in particular allowing use of vector long long (signed and
unsigned) and vector double forms. This patch adds those builtins and
provides documentation for them. There are also cases where builtins
from ISA 2.06 were not added for all possible vector types (for
instance, sometimes defining vector signed long long but omitting vector
unsigned long long). This patch fixes those omissions as well.
I've added a new compile-only test that verifies the new forms are
accepted by the compiler. I've bootstrapped and regtested this on
powerpc64le-unknown-linux-gnu with no regressions, and this new test
passes. Is this ok for trunk?
Thanks,
Bill
[gcc]
2014-08-20 Bill Schmidt
* config/rs6000/altivec.h (vec_cpsgn): New #define.
(vec_mergee): Likewise.
(vec_mergeo): Likewise.
(vec_cntlz): Likewise.
* config/rs600/rs6000-c.c (altivec_overloaded_builtins): Add new
entries for VEC_AND, VEC_ANDC, VEC_MERGEH, VEC_MERGEL, VEC_NOR,
VEC_OR, VEC_PACKSU, VEC_XOR, VEC_PERM, VEC_SEL, VEC_VCMPGT_P,
VMRGEW, and VMRGOW.
* doc/extend.texi: Document various forms of vec_cpsgn,
vec_splats, vec_and, vec_andc, vec_mergeh, vec_mergel, vec_nor,
vec_or, vec_perm, vec_sel, vec_sub, vec_xor, vec_all_eq,
vec_all_ge, vec_all_gt, vec_all_le, vec_all_lt, vec_all_ne,
vec_any_eq, vec_any_ge, vec_any_gt, vec_any_le, vec_any_lt,
vec_any_ne, vec_mergee, vec_mergeo, vec_packsu, and vec_cntlz.
[gcc/testsuite]
2014-08-20 Bill Schmidt
* testsuite/gcc.target/powerpc/builtins-1.c: New test.
Index: gcc/config/rs6000/altivec.h
===
--- gcc/config/rs6000/altivec.h (revision 214242)
+++ gcc/config/rs6000/altivec.h (working copy)
@@ -124,6 +124,7 @@
#define vec_vcfux __builtin_vec_vcfux
#define vec_cts __builtin_vec_cts
#define vec_ctu __builtin_vec_ctu
+#define vec_cpsgn __builtin_vec_copysign
#define vec_expte __builtin_vec_expte
#define vec_floor __builtin_vec_floor
#define vec_loge __builtin_vec_loge
@@ -214,8 +215,10 @@
#define vec_lvsl __builtin_vec_lvsl
#define vec_lvsr __builtin_vec_lvsr
#define vec_max __builtin_vec_max
+#define vec_mergee __builtin_vec_vmrgew
#define vec_mergeh __builtin_vec_mergeh
#define vec_mergel __builtin_vec_mergel
+#define vec_mergeo __builtin_vec_vmrgow
#define vec_min __builtin_vec_min
#define vec_mladd __builtin_vec_mladd
#define vec_msum __builtin_vec_msum
@@ -336,6 +339,7 @@
#define vec_vadduqm __builtin_vec_vadduqm
#define vec_vbpermq __builtin_vec_vbpermq
#define vec_vclz __builtin_vec_vclz
+#define vec_cntlz __builtin_vec_vclz
#define vec_vclzb __builtin_vec_vclzb
#define vec_vclzd __builtin_vec_vclzd
#define vec_vclzh __builtin_vec_vclzh
Index: gcc/config/rs6000/rs6000-c.c
===
--- gcc/config/rs6000/rs6000-c.c(revision 214242)
+++ gcc/config/rs6000/rs6000-c.c(working copy)
@@ -884,6 +884,18 @@ const struct altivec_builtin_types altivec_overloa
{ ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
{ ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
+RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
+ { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
+RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
+ { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
+RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
+ { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
+RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
RS6000_BTI_unsigned_V2DI, 0 },
+ { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
+RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
0 },
+ { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
+RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI,
0 },
+ { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
{ ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
@@ -938,6 +950,18 @@ const struct altivec_builtin_types altivec_overloa
{ ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
{ ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
+RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
+ { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
+RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
+ { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
+RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
+ { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
+RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
RS6000_BTI_unsigned_V2DI, 0 },
+ { ALTIVEC_BUI
