Re: [PATCH], PR target/71186, Fix PowerPC splat error

[Segher Boessenkool]

On Tue, May 31, 2016 at 07:43:22PM -0400, Michael Meissner wrote:
> [gcc]
> 2016-05-31  Michael Meissner  
> 
>   PR target/71186
>   * config/rs6000/vsx.md (xxspltib__nosplit): Add alternatives
>   for loading up all 0's or all 1's.
> 
> [gcc/testsuite]
> 2016-05-31  Michael Meissner  
> 
>   PR target/71186
>   * gcc.target/powerpc/pr71186.c: New test.

Okay for trunk, okay for 6 after the usual soak-in period.

Thanks,


Segher

[PATCH], PR target/71186, Fix PowerPC splat error

[Michael Meissner]

Anton Blanchard found that in some cases, setting V4SImode and V8HImode vector
registers to all 0's or all 1's could cause the compiler issue an 'insn does
not satisfy its constraints' error message.  The reason was, 0/-1 treated
specially, since we can generate them using normal ISA 2.06/2.07 instructions.
I added an alternative, to allow these constants for ISA 3.0.

I did a bootstrap and make check with no regressions on a little endian power8,
and I have a similar run going on a big endian power7 system.  Assuming the
power7 system also had no regressions, is this ok to install in the trunk, and
back ported to GCC 6.2 when the previous ISA 3.0 patches get back ported.

[gcc]
2016-05-31  Michael Meissner  

PR target/71186
* config/rs6000/vsx.md (xxspltib__nosplit): Add alternatives
for loading up all 0's or all 1's.

[gcc/testsuite]
2016-05-31  Michael Meissner  

PR target/71186
* gcc.target/powerpc/pr71186.c: New test.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
Index: gcc/config/rs6000/vsx.md
===
--- gcc/config/rs6000/vsx.md
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/config/rs6000)
(revision 236935)
+++ gcc/config/rs6000/vsx.md(.../gcc/config/rs6000) (working copy)
@@ -776,8 +776,8 @@ (define_insn "xxspltib_v16qi"
   [(set_attr "type" "vecperm")])
 
 (define_insn "xxspltib__nosplit"
-  [(set (match_operand:VSINT_842 0 "vsx_register_operand" "=wa")
-   (match_operand:VSINT_842 1 "xxspltib_constant_nosplit" "wE"))]
+  [(set (match_operand:VSINT_842 0 "vsx_register_operand" "=wa,wa")
+   (match_operand:VSINT_842 1 "xxspltib_constant_nosplit" "jwM,wE"))]
   "TARGET_P9_VECTOR"
 {
   rtx op1 = operands[1];
Index: gcc/testsuite/gcc.target/powerpc/pr71186.c
===
--- gcc/testsuite/gcc.target/powerpc/pr71186.c  (revision 0)
+++ gcc/testsuite/gcc.target/powerpc/pr71186.c  (revision 0)
@@ -0,0 +1,32 @@
+/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power9" } } */
+/* { dg-options "-mcpu=power9 -O2" } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+
+static unsigned short x[(16384/sizeof(unsigned short))] __attribute__ 
((aligned (16)));
+static unsigned short y[(16384/sizeof(unsigned short))] __attribute__ 
((aligned (16)));
+static unsigned short a;
+
+void obfuscate(void *a, ...);
+
+static void __attribute__((noinline)) do_one(void)
+{
+ unsigned long i;
+
+ obfuscate(x, y, );
+
+ for (i = 0; i < (16384/sizeof(unsigned short)); i++)
+  y[i] = a * x[i];
+
+ obfuscate(x, y, );
+}
+
+int main(void)
+{
+ unsigned long i;
+
+ for (i = 0; i < 100; i++)
+  do_one();
+
+ return 0;
+}