Re: [PATCH], PowerPC IEEE 128-bit patch #5
On Tue, Aug 25, 2015 at 7:20 PM, Michael Meissner wrote: > Here is the revised patch. Is it ok to install? > > 2015-08-25 Michael Meissner > > * config/rs6000/predicates.md (int_reg_operand_not_pseudo): New > predicate for only GPR hard registers. > > * config/rs6000/rs6000.md (FP): Add IEEE 128-bit floating point > modes to iterators. Add new iterators for moving 128-bit values in > scalar FPR registers and VSX registers. > (FMOVE128): Likewise. > (FMOVE128_FPR): Likewise. > (FMOVE128_GPR): Likewise. > (FMOVE128_VSX): Likewise. > (FLOAT128_SFDFTF): New iterators for IEEE 128-bit floating point > in VSX registers. > (IFKF): Likewise. > (IBM128): Likewise. > (TFIFKF): Likewise. > (RELOAD): Add IEEE 128-bit floating point modes. > (signbittf2): Convert TF insns to add support for new IEEE 128-bit > floating point in VSX registers modes. > (signbit2, IBM128 iterator): Likewise. > (mov_64bit_dm, FMOVE128_FPR iterator): Likewise. > (mov_32bit, FMOVE128_FPR iterator): Likewise. > (negtf2): Likewise. > (neg2, TFIFKF iterator): Likewise. > (negtf2_internal): Likewise. > (abstf2): Likewise. > (abs2, TFIFKF iterator): Likewise. > (ieee_128bit_negative_zero): New IEEE 128-bit floating point in > VSX insn support for negate, absolute value, and negative absolute > value. > (ieee_128bit_vsx_neg2): Likewise. > (ieee_128bit_vsx_neg2_internal): Likewise. > (ieee_128bit_vsx_abs2): Likewise. > (ieee_128bit_vsx_abs2_internal): Likewise. > (ieee_128bit_vsx_nabs2): Likewise. > (ieee_128bit_vsx_nabs2_internal): Likewise. > (FP128_64): Update pack/unpack 128-bit insns for IEEE 128-bit > floating point in VSX registers. > (unpack_dm): Likewise. > (unpack_nodm): Likewise. > (pack): Likewise. > (unpackv1ti): Likewise. > (unpack, FMOVE128_VSX iterator): Likewise. > (packv1ti): Likewise. > (pack, FMOVE128_VSX iterator): Likewise. The revised patch is okay. Thanks, David
Re: [PATCH], PowerPC IEEE 128-bit patch #5
On Wed, Aug 19, 2015 at 07:41:24AM -0500, Segher Boessenkool wrote:
> On Fri, Aug 14, 2015 at 11:46:03AM -0400, Michael Meissner wrote:
> > +;; Like int_reg_operand, but don't return true for pseudo registers
> > +(define_predicate "int_reg_operand_not_pseudo"
> > + (match_operand 0 "register_operand")
> > +{
> > + if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
> > +return 0;
> > +
> > + if (GET_CODE (op) == SUBREG)
> > +op = SUBREG_REG (op);
> > +
> > + if (!REG_P (op))
> > +return 0;
> > +
> > + if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
> > +return 0;
> > +
> > + return INT_REGNO_P (REGNO (op));
> > +})
>
> Since you use this only once, maybe it is easier (to read, etc.) if you
> just test it there? Hard regs do not get subregs.
I was worried about hard regs appearing before reload, and possibly being
subregs, so I'll remove the SUBREG test.
> > +(define_insn_and_split "ieee_128bit_vsx_neg2"
> > + [(set (match_operand:TFIFKF 0 "register_operand" "=wa")
> > + (neg:TFIFKF (match_operand:TFIFKF 1 "register_operand" "wa")))
> > + (clobber (match_scratch:V16QI 2 "=v"))]
> > + "TARGET_FLOAT128 && FLOAT128_IEEE_P (mode)"
> > + "#"
> > + "&& 1"
> > + [(parallel [(set (match_dup 0)
> > + (neg:TFIFKF (match_dup 1)))
> > + (use (match_dup 2))])]
> > +{
> > + if (GET_CODE (operands[2]) == SCRATCH)
> > +operands[2] = gen_reg_rtx (V16QImode);
> > +
> > + operands[3] = gen_reg_rtx (V16QImode);
> > + emit_insn (gen_ieee_128bit_negative_zero (operands[2]));
> > +}
> > + [(set_attr "length" "8")
> > + (set_attr "type" "vecsimple")])
>
> Where is operands[3] used? I guess that whole line should be deleted?
Good catch. It was from the earlier patch before the fix for PR 67071, which
added better support for vector constants that can be constructed with several
vector operations, including a vector octet shift.
> > +(define_insn "*ieee_128bit_vsx_neg2_internal"
> > + [(set (match_operand:TFIFKF 0 "register_operand" "=wa")
> > + (neg:TFIFKF (match_operand:TFIFKF 1 "register_operand" "wa")))
> > + (use (match_operand:V16QI 2 "register_operand" "=v"))]
> > + "TARGET_FLOAT128"
> > + "xxlxor %x0,%x1,%x2"
> > + [(set_attr "length" "4")
> > + (set_attr "type" "vecsimple")])
>
> Length 4 is default, you can just leave it out (like we do for most
> machine insns already).
Ok, though I tend to always put them in.
Here is the revised patch. Is it ok to install?
2015-08-25 Michael Meissner
* config/rs6000/predicates.md (int_reg_operand_not_pseudo): New
predicate for only GPR hard registers.
* config/rs6000/rs6000.md (FP): Add IEEE 128-bit floating point
modes to iterators. Add new iterators for moving 128-bit values in
scalar FPR registers and VSX registers.
(FMOVE128): Likewise.
(FMOVE128_FPR): Likewise.
(FMOVE128_GPR): Likewise.
(FMOVE128_VSX): Likewise.
(FLOAT128_SFDFTF): New iterators for IEEE 128-bit floating point
in VSX registers.
(IFKF): Likewise.
(IBM128): Likewise.
(TFIFKF): Likewise.
(RELOAD): Add IEEE 128-bit floating point modes.
(signbittf2): Convert TF insns to add support for new IEEE 128-bit
floating point in VSX registers modes.
(signbit2, IBM128 iterator): Likewise.
(mov_64bit_dm, FMOVE128_FPR iterator): Likewise.
(mov_32bit, FMOVE128_FPR iterator): Likewise.
(negtf2): Likewise.
(neg2, TFIFKF iterator): Likewise.
(negtf2_internal): Likewise.
(abstf2): Likewise.
(abs2, TFIFKF iterator): Likewise.
(ieee_128bit_negative_zero): New IEEE 128-bit floating point in
VSX insn support for negate, absolute value, and negative absolute
value.
(ieee_128bit_vsx_neg2): Likewise.
(ieee_128bit_vsx_neg2_internal): Likewise.
(ieee_128bit_vsx_abs2): Likewise.
(ieee_128bit_vsx_abs2_internal): Likewise.
(ieee_128bit_vsx_nabs2): Likewise.
(ieee_128bit_vsx_nabs2_internal): Likewise.
(FP128_64): Update pack/unpack 128-bit insns for IEEE 128-bit
floating point in VSX registers.
(unpack_dm): Likewise.
(unpack_nodm): Likewise.
(pack): Likewise.
(unpackv1ti): Likewise.
(unpack, FMOVE128_VSX iterator): Likewise.
(packv1ti): Likewise.
(pack, FMOVE128_VSX iterator): Likewise.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
Index: gcc/config/rs6000/predicates.md
===
--- gcc/config/rs6000/predicates.md (revision 227180)
+++ gcc/config/rs6000/predicates.md (working copy)
@@ -239,6 +239,25 @@ (define_predicate "int_reg_operand"
return INT_REGNO_P (REGNO (op));
})
+;; Like int_reg_operand, but don't return true for pseudo regi
Re: [PATCH], PowerPC IEEE 128-bit patch #5
On Fri, Aug 14, 2015 at 11:46:03AM -0400, Michael Meissner wrote:
> +;; Like int_reg_operand, but don't return true for pseudo registers
> +(define_predicate "int_reg_operand_not_pseudo"
> + (match_operand 0 "register_operand")
> +{
> + if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
> +return 0;
> +
> + if (GET_CODE (op) == SUBREG)
> +op = SUBREG_REG (op);
> +
> + if (!REG_P (op))
> +return 0;
> +
> + if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
> +return 0;
> +
> + return INT_REGNO_P (REGNO (op));
> +})
Since you use this only once, maybe it is easier (to read, etc.) if you
just test it there? Hard regs do not get subregs.
> +(define_insn_and_split "ieee_128bit_vsx_neg2"
> + [(set (match_operand:TFIFKF 0 "register_operand" "=wa")
> + (neg:TFIFKF (match_operand:TFIFKF 1 "register_operand" "wa")))
> + (clobber (match_scratch:V16QI 2 "=v"))]
> + "TARGET_FLOAT128 && FLOAT128_IEEE_P (mode)"
> + "#"
> + "&& 1"
> + [(parallel [(set (match_dup 0)
> +(neg:TFIFKF (match_dup 1)))
> + (use (match_dup 2))])]
> +{
> + if (GET_CODE (operands[2]) == SCRATCH)
> +operands[2] = gen_reg_rtx (V16QImode);
> +
> + operands[3] = gen_reg_rtx (V16QImode);
> + emit_insn (gen_ieee_128bit_negative_zero (operands[2]));
> +}
> + [(set_attr "length" "8")
> + (set_attr "type" "vecsimple")])
Where is operands[3] used? I guess that whole line should be deleted?
> +(define_insn "*ieee_128bit_vsx_neg2_internal"
> + [(set (match_operand:TFIFKF 0 "register_operand" "=wa")
> + (neg:TFIFKF (match_operand:TFIFKF 1 "register_operand" "wa")))
> + (use (match_operand:V16QI 2 "register_operand" "=v"))]
> + "TARGET_FLOAT128"
> + "xxlxor %x0,%x1,%x2"
> + [(set_attr "length" "4")
> + (set_attr "type" "vecsimple")])
Length 4 is default, you can just leave it out (like we do for most
machine insns already).
Segher
Re: [PATCH], PowerPC IEEE 128-bit patch #5
There are 3 patches left in the basic IEEE 128-bit floating point support for
the compiler. I will submit these at the same time. They are split to make the
review process similar. Patch #5 and #6 are indpendent of each other and can
be applied in either order. Patch #7 assumes that patches 1-6 have been
applied.
Patch #5 adds the following:
* Support for the reload handlers that will be enabled in patch #7.
* Adds IFmode/KFmode to other iterators as appropriate.
* Adds the basic negate, absolute value, and negative absolute value support.
* Adds the insns for the 128-bit pack/unpack routines.
Patch #6 adds the following:
* Adds support for comparisons.
* Updates the cannot change mode support.
Patch #7 finishes up the initial basic support.
* It defines macros for IEEE 128-bit floating point users.
* It defines the basic move support.
* It sets up the calling sequence.
* It registers the __float128 and __ibm128 keywords.
* It sets up the various handler functions.
* It adds 'q' and 'Q' as the suffix for IEEE 128-bit floating point.
* It adds target attribute/pragma support for the IEEE 128-bit options.
* It treats IEEE 128-bit in VSX register modes as vector.
* It uses a unique mangling for IEEE 128-bit in VSX registers.
* It moves vector modes tieable above scalar floating point.
* It adds a simple minded test to make sure IEEE args are passed as vectors.
Things to be done:
* Work with GDB to add debug support.
* Work with GLIBC to add basic software emulation support.
* Work with GLIBC on other IEEE 128-bit support.
* Look into Complex support.
* Look into libquadmath support.
* Enable -mfloat128-software if -mvsx.
* Add more tests.
* Fix bugs that show up if -mabi=ieeelongdouble is used.
Each patch bootstraps without error and has no regressions. Are they ok to
install in the trunk?
This is patch #5:
2015-08-13 Michael Meissner
* config/rs6000/predicates.md (int_reg_operand_not_pseudo): New
predicate for only GPR hard registers.
* config/rs6000/rs6000.md (FP): Add IEEE 128-bit floating point
modes to iterators. Add new iterators for moving 128-bit values in
scalar FPR registers and VSX registers.
(FMOVE128): Likewise.
(FMOVE128_FPR): Likewise.
(FMOVE128_GPR): Likewise.
(FMOVE128_VSX): Likewise.
(FLOAT128_SFDFTF): New iterators for IEEE 128-bit floating point
in VSX registers.
(IFKF): Likewise.
(IBM128): Likewise.
(TFIFKF): Likewise.
(RELOAD): Add IEEE 128-bit floating point modes.
(signbittf2): Convert TF insns to add support for new IEEE 128-bit
floating point in VSX registers modes.
(signbit2, IBM128 iterator): Likewise.
(mov_64bit_dm, FMOVE128_FPR iterator): Likewise.
(mov_32bit, FMOVE128_FPR iterator): Likewise.
(negtf2): Likewise.
(neg2, TFIFKF iterator): Likewise.
(negtf2_internal): Likewise.
(abstf2): Likewise.
(abs2, TFIFKF iterator): Likewise.
(ieee_128bit_negative_zero): New IEEE 128-bit floating point in
VSX insn support for negate, absolute value, and negative absolute
value.
(ieee_128bit_vsx_neg2): Likewise.
(ieee_128bit_vsx_neg2_internal): Likewise.
(ieee_128bit_vsx_abs2): Likewise.
(ieee_128bit_vsx_abs2_internal): Likewise.
(ieee_128bit_vsx_nabs2): Likewise.
(ieee_128bit_vsx_nabs2_internal): Likewise.
(FP128_64): Update pack/unpack 128-bit insns for IEEE 128-bit
floating point in VSX registers.
(unpack_dm): Likewise.
(unpack_nodm): Likewise.
(pack): Likewise.
(unpackv1ti): Likewise.
(unpack, FMOVE128_VSX iterator): Likewise.
(packv1ti): Likewise.
(pack, FMOVE128_VSX iterator): Likewise.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
Index: gcc/config/rs6000/predicates.md
===
--- gcc/config/rs6000/predicates.md (revision 226869)
+++ gcc/config/rs6000/predicates.md (working copy)
@@ -239,6 +239,25 @@ (define_predicate "int_reg_operand"
return INT_REGNO_P (REGNO (op));
})
+;; Like int_reg_operand, but don't return true for pseudo registers
+(define_predicate "int_reg_operand_not_pseudo"
+ (match_operand 0 "register_operand")
+{
+ if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
+return 0;
+
+ if (GET_CODE (op) == SUBREG)
+op = SUBREG_REG (op);
+
+ if (!REG_P (op))
+return 0;
+
+ if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
+return 0;
+
+ return INT_REGNO_P (REGNO (op));
+})
+
;; Like int_reg_operand, but only return true for base registers
(define_predicate "base_reg_operand"
(match_operand 0 "int_reg_operand")
Index: gcc/config/rs6000/rs6000.md
=
