Hi all,
This patch fixes the test gcc.target/aarch64/pr66776.c for -mcpu=cortex-a53.
Currently we don't handle the (if_then_else (cond) (zero_extend r1)
(zero_extend r2))
form of CSEL, so we end up recursing into the operands of the if_then_else and
for some CPUs
reject the combination. We end up generating two UXTW instructions followed by
a CSEL rather
than a single CSEL on the w-regs. Such is the case for -mcpu=cortex-a53.
This small patch fixes that by catching the zero_extended operands and
extracting their
inner regs properly for further costing in aarch64_if_then_else_costs.
With this patch the aforementioned test now passes with -mcpu=cortex-a53.
Bootstrapped and tested on aarch64-none-linux-gnu.
Ok for trunk?
Thanks,
Kyrill
2016-01-11 Kyrylo Tkachov
* config/aarch64/aarch64.c (aarch64_if_then_else_costs): Handle
CSEL of zero_extended registers.
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 509d2115934a20e9e747d86249586f06b4b3a432..9474f51c948aeaa4260f6e979728aa9b0b490bb8 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -6136,6 +6136,12 @@ aarch64_if_then_else_costs (rtx op0, rtx op1, rtx op2, int *cost, bool speed)
|| GET_CODE (op1) == NOT
|| (GET_CODE (op1) == PLUS && XEXP (op1, 1) == const1_rtx))
op1 = XEXP (op1, 0);
+ else if (GET_CODE (op1) == ZERO_EXTEND && GET_CODE (op2) == ZERO_EXTEND)
+ {
+ /* CSEL with zero-extension (*cmovdi_insn_uxtw). */
+ op1 = XEXP (op1, 0);
+ op2 = XEXP (op2, 0);
+ }
*cost += rtx_cost (op1, VOIDmode, IF_THEN_ELSE, 1, speed);
*cost += rtx_cost (op2, VOIDmode, IF_THEN_ELSE, 2, speed);