This patch marks a rev16 test as XFAIL for architectures having only
Thumb1 support. The generated code is functionally correct, but the
optimization is disabled when -mthumb is equivalent to Thumb1. Fixing
the root issue would requires changes that are not suitable for GCC14
stage 4.
More information at https://linaro.atlassian.net/browse/GNU-1141
gcc/testsuite/ChangeLog:
* gcc.target/arm/rev16_2.c: XFAIL when compiled with Thumb1.From 11be6a0feb1cbc0bca6e23dacf98c5817b71ba3d Mon Sep 17 00:00:00 2001
From: Matthieu Longo
Date: Thu, 8 Feb 2024 18:13:49 +
Subject: [PATCH] [arm] Missing optimization pattern for rev16 on architectures
with thumb1.
This patch marks a rev16 test as XFAIL for architectures having only Thumb1
support. The generated code is functionally correct, but the optimization is
disabled when -mthumb is equivalent to Thumb1. Fixing the root issue would
requires changes that are not suitable for GCC14 stage 4.
More information at https://linaro.atlassian.net/browse/GNU-1141
gcc/testsuite/ChangeLog:
* gcc.target/arm/rev16_2.c: XFAIL when compiled with Thumb1.
---
gcc/testsuite/gcc.target/arm/rev16_2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/arm/rev16_2.c
b/gcc/testsuite/gcc.target/arm/rev16_2.c
index c6553b38a00..dff66e10bb9 100644
--- a/gcc/testsuite/gcc.target/arm/rev16_2.c
+++ b/gcc/testsuite/gcc.target/arm/rev16_2.c
@@ -17,4 +17,4 @@ __rev16_32 (__u32 x)
| (((__u32)(x) & (__u32)0xff00ff00UL) >> 8);
}
-/* { dg-final { scan-assembler-times {rev16\tr[0-9]+, r[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {rev16\tr[0-9]+, r[0-9]+} 2 { xfail
arm_thumb1_ok } } } */
\ No newline at end of file
--
2.34.1