[PATCH] LoongArch: Optimizations of vector construction.
Change-Id: I327f68ab482b94073974e672c71d25c98b35a080 gcc/ChangeLog: * config/loongarch/lasx.md (lasx_vecinit_merge_): New pattern for vector construction. (vec_set_internal): Ditto. (lasx_xvinsgr2vr__internal): Ditto. (lasx_xvilvl__internal): Ditto. * config/loongarch/loongarch.cc (loongarch_expand_vector_init): Optimized the implementation of vector construction. (loongarch_expand_vector_init_same): New function. * config/loongarch/lsx.md (lsx_vilvl__internal): New pattern for vector construction. (lsx_vreplvei_mirror_): New pattern for vector construction. (vec_concatv2df): Ditto. (vec_concatv4sf): Ditto. gcc/testsuite/ChangeLog: * gcc.target/loongarch/vector/lasx/lasx-vec-construct-opt.c: New test. * gcc.target/loongarch/vector/lsx/lsx-vec-construct-opt.c: New test. --- gcc/config/loongarch/lasx.md | 69 ++ gcc/config/loongarch/loongarch.cc | 716 +- gcc/config/loongarch/lsx.md | 134 .../vector/lasx/lasx-vec-construct-opt.c | 102 +++ .../vector/lsx/lsx-vec-construct-opt.c| 85 +++ 5 files changed, 732 insertions(+), 374 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-vec-construct-opt.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vec-construct-opt.c diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md index 8111c8bb79a..2bc5d47ed4a 100644 --- a/gcc/config/loongarch/lasx.md +++ b/gcc/config/loongarch/lasx.md @@ -186,6 +186,9 @@ (define_c_enum "unspec" [ UNSPEC_LASX_XVLDI UNSPEC_LASX_XVLDX UNSPEC_LASX_XVSTX + UNSPEC_LASX_VECINIT_MERGE + UNSPEC_LASX_VEC_SET_INTERNAL + UNSPEC_LASX_XVILVL_INTERNAL ]) ;; All vector modes with 256 bits. @@ -255,6 +258,15 @@ (define_mode_attr VFHMODE256 [(V8SF "V4SF") (V4DF "V2DF")]) +;; The attribute gives half int/float modes for vector modes. +(define_mode_attr VHMODE256_ALL + [(V32QI "V16QI") + (V16HI "V8HI") + (V8SI "V4SI") + (V4DI "V2DI") + (V8SF "V4SF") + (V4DF "V2DF")]) + ;; The attribute gives double modes for vector modes in LASX. (define_mode_attr VDMODE256 [(V8SI "V4DI") @@ -312,6 +324,11 @@ (define_mode_attr mode256_f (V4DI "v4df") (V8SI "v8sf")]) +;; This attribute gives V32QI mode and V16HI mode with half size. +(define_mode_attr mode256_i_half + [(V32QI "v16qi") + (V16HI "v8hi")]) + ;; This attribute gives suffix for LASX instructions. HOW? (define_mode_attr lasxfmt [(V4DF "d") @@ -756,6 +773,20 @@ (define_insn "lasx_xvpermi_q_" [(set_attr "type" "simd_splat") (set_attr "mode" "")]) +;; Only for loongarch_expand_vector_init in loongarch.cc. +;; Support a LSX-mode input op2. +(define_insn "lasx_vecinit_merge_" + [(set (match_operand:LASX 0 "register_operand" "=f") + (unspec:LASX + [(match_operand:LASX 1 "register_operand" "0") + (match_operand: 2 "register_operand" "f") + (match_operand 3 "const_uimm8_operand")] + UNSPEC_LASX_VECINIT_MERGE))] + "ISA_HAS_LASX" + "xvpermi.q\t%u0,%u2,%3" + [(set_attr "type" "simd_splat") + (set_attr "mode" "")]) + (define_insn "lasx_xvpickve2gr_d" [(set (match_operand:DI 0 "register_operand" "=r") (any_extend:DI @@ -779,6 +810,33 @@ (define_expand "vec_set" DONE; }) +;; Only for loongarch_expand_vector_init in loongarch.cc. +;; Simulate missing instructions xvinsgr2vr.b and xvinsgr2vr.h. +(define_expand "vec_set_internal" + [(match_operand:ILASX_HB 0 "register_operand") + (match_operand: 1 "reg_or_0_operand") + (match_operand 2 "const__operand")] + "ISA_HAS_LASX" +{ + rtx index = GEN_INT (1 << INTVAL (operands[2])); + emit_insn (gen_lasx_xvinsgr2vr__internal +(operands[0], operands[1], operands[0], index)); + DONE; +}) + +(define_insn "lasx_xvinsgr2vr__internal" + [(set (match_operand:ILASX_HB 0 "register_operand" "=f") + (unspec:ILASX_HB [(match_operand: 1 "reg_or_0_operand" "rJ") + (match_operand:ILASX_HB 2 "register_operand" "0") + (match_operand 3 "const__operand" "")] +UNSPEC_LASX_VEC_SET_INTERNAL))] + "ISA_HAS_LASX" +{ + return "vinsgr2vr.\t%w0,%z1,%y3"; +} + [(set_attr "type" "simd_insert") + (set_attr "mode" "")]) + (define_expand "vec_set" [(match_operand:FLASX 0 "register_operand") (match_operand: 1 "reg_or_0_operand") @@ -1567,6 +1625,17 @@ (define_insn "logb2" [(set_attr "type" "simd_flog2") (set_attr "mode" "")]) +;; Only for loongarch_expand_vector_init in loongarch.cc. +;; Merge two scalar floating-point op1 and op2 into a LASX op0. +(define_insn "lasx_xvilvl__internal" + [(set (match_operand:FLASX 0 "register_operand" "=f") + (unspec:FLASX [(match_operand: 1 "register_operand" "f") + (match_operand: 2 "register_operand" "f")] +
[PATCH] LoongArch: Optimizations of vector construction.
gcc/ChangeLog: * config/loongarch/lasx.md (lasx_vecinit_merge_): New pattern for vector construction. (vec_set_internal): Ditto. (lasx_xvinsgr2vr__internal): Ditto. (lasx_xvilvl__internal): Ditto. * config/loongarch/loongarch.cc (loongarch_expand_vector_init): Optimized the implementation of vector construction. (loongarch_expand_vector_init_same): New function. * config/loongarch/lsx.md (lsx_vilvl__internal): New pattern for vector construction. (lsx_vreplvei_mirror_): New pattern for vector construction. (vec_concatv2df): Ditto. (vec_concatv4sf): Ditto. gcc/testsuite/ChangeLog: * gcc.target/loongarch/vector/lasx/lasx-vec-construct-opt.c: New test. * gcc.target/loongarch/vector/lsx/lsx-vec-construct-opt.c: New test. --- gcc/config/loongarch/lasx.md | 69 ++ gcc/config/loongarch/loongarch.cc | 716 +- gcc/config/loongarch/lsx.md | 134 .../vector/lasx/lasx-vec-construct-opt.c | 102 +++ .../vector/lsx/lsx-vec-construct-opt.c| 85 +++ 5 files changed, 732 insertions(+), 374 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-vec-construct-opt.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vec-construct-opt.c diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md index 8111c8bb79a..2bc5d47ed4a 100644 --- a/gcc/config/loongarch/lasx.md +++ b/gcc/config/loongarch/lasx.md @@ -186,6 +186,9 @@ (define_c_enum "unspec" [ UNSPEC_LASX_XVLDI UNSPEC_LASX_XVLDX UNSPEC_LASX_XVSTX + UNSPEC_LASX_VECINIT_MERGE + UNSPEC_LASX_VEC_SET_INTERNAL + UNSPEC_LASX_XVILVL_INTERNAL ]) ;; All vector modes with 256 bits. @@ -255,6 +258,15 @@ (define_mode_attr VFHMODE256 [(V8SF "V4SF") (V4DF "V2DF")]) +;; The attribute gives half int/float modes for vector modes. +(define_mode_attr VHMODE256_ALL + [(V32QI "V16QI") + (V16HI "V8HI") + (V8SI "V4SI") + (V4DI "V2DI") + (V8SF "V4SF") + (V4DF "V2DF")]) + ;; The attribute gives double modes for vector modes in LASX. (define_mode_attr VDMODE256 [(V8SI "V4DI") @@ -312,6 +324,11 @@ (define_mode_attr mode256_f (V4DI "v4df") (V8SI "v8sf")]) +;; This attribute gives V32QI mode and V16HI mode with half size. +(define_mode_attr mode256_i_half + [(V32QI "v16qi") + (V16HI "v8hi")]) + ;; This attribute gives suffix for LASX instructions. HOW? (define_mode_attr lasxfmt [(V4DF "d") @@ -756,6 +773,20 @@ (define_insn "lasx_xvpermi_q_" [(set_attr "type" "simd_splat") (set_attr "mode" "")]) +;; Only for loongarch_expand_vector_init in loongarch.cc. +;; Support a LSX-mode input op2. +(define_insn "lasx_vecinit_merge_" + [(set (match_operand:LASX 0 "register_operand" "=f") + (unspec:LASX + [(match_operand:LASX 1 "register_operand" "0") + (match_operand: 2 "register_operand" "f") + (match_operand 3 "const_uimm8_operand")] + UNSPEC_LASX_VECINIT_MERGE))] + "ISA_HAS_LASX" + "xvpermi.q\t%u0,%u2,%3" + [(set_attr "type" "simd_splat") + (set_attr "mode" "")]) + (define_insn "lasx_xvpickve2gr_d" [(set (match_operand:DI 0 "register_operand" "=r") (any_extend:DI @@ -779,6 +810,33 @@ (define_expand "vec_set" DONE; }) +;; Only for loongarch_expand_vector_init in loongarch.cc. +;; Simulate missing instructions xvinsgr2vr.b and xvinsgr2vr.h. +(define_expand "vec_set_internal" + [(match_operand:ILASX_HB 0 "register_operand") + (match_operand: 1 "reg_or_0_operand") + (match_operand 2 "const__operand")] + "ISA_HAS_LASX" +{ + rtx index = GEN_INT (1 << INTVAL (operands[2])); + emit_insn (gen_lasx_xvinsgr2vr__internal +(operands[0], operands[1], operands[0], index)); + DONE; +}) + +(define_insn "lasx_xvinsgr2vr__internal" + [(set (match_operand:ILASX_HB 0 "register_operand" "=f") + (unspec:ILASX_HB [(match_operand: 1 "reg_or_0_operand" "rJ") + (match_operand:ILASX_HB 2 "register_operand" "0") + (match_operand 3 "const__operand" "")] +UNSPEC_LASX_VEC_SET_INTERNAL))] + "ISA_HAS_LASX" +{ + return "vinsgr2vr.\t%w0,%z1,%y3"; +} + [(set_attr "type" "simd_insert") + (set_attr "mode" "")]) + (define_expand "vec_set" [(match_operand:FLASX 0 "register_operand") (match_operand: 1 "reg_or_0_operand") @@ -1567,6 +1625,17 @@ (define_insn "logb2" [(set_attr "type" "simd_flog2") (set_attr "mode" "")]) +;; Only for loongarch_expand_vector_init in loongarch.cc. +;; Merge two scalar floating-point op1 and op2 into a LASX op0. +(define_insn "lasx_xvilvl__internal" + [(set (match_operand:FLASX 0 "register_operand" "=f") + (unspec:FLASX [(match_operand: 1 "register_operand" "f") + (match_operand: 2 "register_operand" "f")] + UNSPEC_LASX_XVILVL_INTERNAL))] + "ISA_H
Re:[pushed] [PATCH] LoongArch: Optimizations of vector construction.
Pushed to r14-4245. 在 2023/9/21 上午9:19, Guo Jie 写道: gcc/ChangeLog: * config/loongarch/lasx.md (lasx_vecinit_merge_): New pattern for vector construction. (vec_set_internal): Ditto. (lasx_xvinsgr2vr__internal): Ditto. (lasx_xvilvl__internal): Ditto. * config/loongarch/loongarch.cc (loongarch_expand_vector_init): Optimized the implementation of vector construction. (loongarch_expand_vector_init_same): New function. * config/loongarch/lsx.md (lsx_vilvl__internal): New pattern for vector construction. (lsx_vreplvei_mirror_): New pattern for vector construction. (vec_concatv2df): Ditto. (vec_concatv4sf): Ditto. gcc/testsuite/ChangeLog: * gcc.target/loongarch/vector/lasx/lasx-vec-construct-opt.c: New test. * gcc.target/loongarch/vector/lsx/lsx-vec-construct-opt.c: New test. --- gcc/config/loongarch/lasx.md | 69 ++ gcc/config/loongarch/loongarch.cc | 716 +- gcc/config/loongarch/lsx.md | 134 .../vector/lasx/lasx-vec-construct-opt.c | 102 +++ .../vector/lsx/lsx-vec-construct-opt.c| 85 +++ 5 files changed, 732 insertions(+), 374 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-vec-construct-opt.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vec-construct-opt.c diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md index 8111c8bb79a..2bc5d47ed4a 100644 --- a/gcc/config/loongarch/lasx.md +++ b/gcc/config/loongarch/lasx.md @@ -186,6 +186,9 @@ (define_c_enum "unspec" [ UNSPEC_LASX_XVLDI UNSPEC_LASX_XVLDX UNSPEC_LASX_XVSTX + UNSPEC_LASX_VECINIT_MERGE + UNSPEC_LASX_VEC_SET_INTERNAL + UNSPEC_LASX_XVILVL_INTERNAL ]) ;; All vector modes with 256 bits. @@ -255,6 +258,15 @@ (define_mode_attr VFHMODE256 [(V8SF "V4SF") (V4DF "V2DF")]) +;; The attribute gives half int/float modes for vector modes. +(define_mode_attr VHMODE256_ALL + [(V32QI "V16QI") + (V16HI "V8HI") + (V8SI "V4SI") + (V4DI "V2DI") + (V8SF "V4SF") + (V4DF "V2DF")]) + ;; The attribute gives double modes for vector modes in LASX. (define_mode_attr VDMODE256 [(V8SI "V4DI") @@ -312,6 +324,11 @@ (define_mode_attr mode256_f (V4DI "v4df") (V8SI "v8sf")]) +;; This attribute gives V32QI mode and V16HI mode with half size. +(define_mode_attr mode256_i_half + [(V32QI "v16qi") + (V16HI "v8hi")]) + ;; This attribute gives suffix for LASX instructions. HOW? (define_mode_attr lasxfmt [(V4DF "d") @@ -756,6 +773,20 @@ (define_insn "lasx_xvpermi_q_" [(set_attr "type" "simd_splat") (set_attr "mode" "")]) +;; Only for loongarch_expand_vector_init in loongarch.cc. +;; Support a LSX-mode input op2. +(define_insn "lasx_vecinit_merge_" + [(set (match_operand:LASX 0 "register_operand" "=f") + (unspec:LASX + [(match_operand:LASX 1 "register_operand" "0") + (match_operand: 2 "register_operand" "f") + (match_operand 3 "const_uimm8_operand")] + UNSPEC_LASX_VECINIT_MERGE))] + "ISA_HAS_LASX" + "xvpermi.q\t%u0,%u2,%3" + [(set_attr "type" "simd_splat") + (set_attr "mode" "")]) + (define_insn "lasx_xvpickve2gr_d" [(set (match_operand:DI 0 "register_operand" "=r") (any_extend:DI @@ -779,6 +810,33 @@ (define_expand "vec_set" DONE; }) +;; Only for loongarch_expand_vector_init in loongarch.cc. +;; Simulate missing instructions xvinsgr2vr.b and xvinsgr2vr.h. +(define_expand "vec_set_internal" + [(match_operand:ILASX_HB 0 "register_operand") + (match_operand: 1 "reg_or_0_operand") + (match_operand 2 "const__operand")] + "ISA_HAS_LASX" +{ + rtx index = GEN_INT (1 << INTVAL (operands[2])); + emit_insn (gen_lasx_xvinsgr2vr__internal +(operands[0], operands[1], operands[0], index)); + DONE; +}) + +(define_insn "lasx_xvinsgr2vr__internal" + [(set (match_operand:ILASX_HB 0 "register_operand" "=f") + (unspec:ILASX_HB [(match_operand: 1 "reg_or_0_operand" "rJ") + (match_operand:ILASX_HB 2 "register_operand" "0") + (match_operand 3 "const__operand" "")] +UNSPEC_LASX_VEC_SET_INTERNAL))] + "ISA_HAS_LASX" +{ + return "vinsgr2vr.\t%w0,%z1,%y3"; +} + [(set_attr "type" "simd_insert") + (set_attr "mode" "")]) + (define_expand "vec_set" [(match_operand:FLASX 0 "register_operand") (match_operand: 1 "reg_or_0_operand") @@ -1567,6 +1625,17 @@ (define_insn "logb2" [(set_attr "type" "simd_flog2") (set_attr "mode" "")]) +;; Only for loongarch_expand_vector_init in loongarch.cc. +;; Merge two scalar floating-point op1 and op2 into a LASX op0. +(define_insn "lasx_xvilvl__internal" + [(set (match_operand:FLASX 0 "register_operand" "=f") + (unspec:FLASX [(match_operand: 1 "register_operand" "f") + (mat