Re: [PATCH] PowerPC: Reformat move insns to make them clearing, patch #1 of 5

[Segher Boessenkool]

On Thu, May 03, 2018 at 02:10:50PM -0400, Michael Meissner wrote:
> 2018-05-03  Michael Meissner  
> 
>   * config/rs6000/rs6000.md (mov_hardfloat32, FMOVE64):
>   Reformat alternatives and attributes so it is easier to identify
>   which constraints/attributes go with which instruction.

This is fine, thanks!


Segher

[PATCH] PowerPC: Reformat move insns to make them clearing, patch #1 of 5

[Michael Meissner]

These patches were previously posted in March as RFC's.  These patches just
reformat the floating point move insns to make it easier to figure out which
constraints and attributes are used for particular alternatives.

I have built the compiler on a little endian power8 system with all 5 patches
applied and it bootstraps without error.  There were no regressions in make
check output. Can I check these patches in?

This is patch #1 of 5.

2018-05-03  Michael Meissner  

* config/rs6000/rs6000.md (mov_hardfloat32, FMOVE64):
Reformat alternatives and attributes so it is easier to identify
which constraints/attributes go with which instruction.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.ibm.com, phone: +1 (978) 899-4797
Index: gcc/config/rs6000/rs6000.md
===
--- gcc/config/rs6000/rs6000.md (revision 259864)
+++ gcc/config/rs6000/rs6000.md (working copy)
@@ -7388,9 +7388,21 @@ (define_split
 ;; If we have FPR registers, rs6000_emit_move has moved all constants to 
memory,
 ;; except for 0.0 which can be created on VSX with an xor instruction.
 
+;;   STFD LFD FMR LXSDSTXSD
+;;   LXSD STXSD   XXLOR   XXLXOR  GPR<-0
+;;   LWZ  STW MR
+
 (define_insn "*mov_hardfloat32"
-  [(set (match_operand:FMOVE64 0 "nonimmediate_operand" 
"=m,d,d,,wY,,Z,,,!r,Y,r,!r")
-   (match_operand:FMOVE64 1 "input_operand" 
"d,m,d,wY,,Z,r,Y,r"))]
+  [(set (match_operand:FMOVE64 0 "nonimmediate_operand"
+"=m,  d,  d,  ,   wY,
+  ,   Z,  ,  ,  !r,
+  Y,  r,  !r")
+
+   (match_operand:FMOVE64 1 "input_operand"
+ "d,  m,  d,  wY, ,
+  Z,  ,   ,  ,  ,
+  r,  Y,  r"))]
+
   "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT 
&& (gpc_reg_operand (operands[0], mode)
|| gpc_reg_operand (operands[1], mode))"
@@ -7408,9 +7420,16 @@ (define_insn "*mov_hardfloat32"
#
#
#"
-  [(set_attr "type" 
"fpstore,fpload,fpsimple,fpload,fpstore,fpload,fpstore,veclogical,veclogical,two,store,load,two")
+  [(set_attr "type"
+"fpstore, fpload, fpsimple,   fpload, fpstore,
+ fpload,  fpstore,veclogical, veclogical, two,
+ store,   load,   two")
+
(set_attr "size" "64")
-   (set_attr "length" "4,4,4,4,4,4,4,4,4,8,8,8,8")])
+   (set_attr "length"
+"4,   4,  4,  4,  4,
+ 4,   4,  4,  4,  8,
+ 8,   8,  8")])
 
 (define_insn "*mov_softfloat32"
   [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")