Re: Re: [PATCH] RISC-V: Add RISC-V into vect_cmdline_needed
Thanks. Committed. juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-11-07 20:10 To: juzhe.zh...@rivai.ai; gcc-patches CC: rdapp.gcc; kito.cheng; Kito.cheng; jeffreyalaw Subject: Re: [PATCH] RISC-V: Add RISC-V into vect_cmdline_needed > It need command line to enable SIMD auto-vectorization (VLS mode in RVV). > It will enable VLS modes auto-vectorization by default if we didn't add RISCV > into vect_cmdline. > So adding it to disable VLS mode vectorization which will fix the FAILs like > other targets. Ah so it's about SIMD despite the name, I see. Still weird but adding riscv then makes sense. So OK. The test probably just very old. Regards Robin
Re: [PATCH] RISC-V: Add RISC-V into vect_cmdline_needed
> It need command line to enable SIMD auto-vectorization (VLS mode in RVV). > It will enable VLS modes auto-vectorization by default if we didn't add RISCV > into vect_cmdline. > So adding it to disable VLS mode vectorization which will fix the FAILs like > other targets. Ah so it's about SIMD despite the name, I see. Still weird but adding riscv then makes sense. So OK. The test probably just very old. Regards Robin
Re: Re: [PATCH] RISC-V: Add RISC-V into vect_cmdline_needed
It need command line to enable SIMD auto-vectorization (VLS mode in RVV). It will enable VLS modes auto-vectorization by default if we didn't add RISCV into vect_cmdline. So adding it to disable VLS mode vectorization which will fix the FAILs like other targets. juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-11-07 20:04 To: Juzhe-Zhong; gcc-patches CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw Subject: Re: [PATCH] RISC-V: Add RISC-V into vect_cmdline_needed Looks OK but I don't really get the test (e.g. gen-vect-26.c). It is only ran if target vect_cmdline_needed, otherwise compiled? Why does that have an impact on the scan? Looks weird but well... Regards Robin
Re: [PATCH] RISC-V: Add RISC-V into vect_cmdline_needed
Looks OK but I don't really get the test (e.g. gen-vect-26.c). It is only ran if target vect_cmdline_needed, otherwise compiled? Why does that have an impact on the scan? Looks weird but well... Regards Robin
[PATCH] RISC-V: Add RISC-V into vect_cmdline_needed
Like all other targets, we add RISC-V into vect_cmdline_needed.
This patch fixes following FAILs:
FAIL: gcc.dg/tree-ssa/gen-vect-11b.c scan-tree-dump-times vect "vectorized 0
loops" 1
FAIL: gcc.dg/tree-ssa/gen-vect-11c.c scan-tree-dump-times vect "vectorized 0
loops" 1
FAIL: gcc.dg/tree-ssa/gen-vect-26.c scan-tree-dump-times vect "Alignment of
access forced using peeling" 1
FAIL: gcc.dg/tree-ssa/gen-vect-28.c scan-tree-dump-times vect "Alignment of
access forced using peeling" 1
gcc/testsuite/ChangeLog:
* lib/target-supports.exp: Add RISC-V.
---
gcc/testsuite/lib/target-supports.exp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 17a87db0007..285817ef16e 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -4036,7 +4036,8 @@ proc check_effective_target_vect_cmdline_needed { } {
|| ([istarget sparc*-*-*] && [check_effective_target_sparc_vis])
|| ([istarget arm*-*-*] && [check_effective_target_arm_neon])
|| [istarget aarch64*-*-*]
- || [istarget amdgcn*-*-*]} {
+|| [istarget amdgcn*-*-*]
+|| [istarget riscv*-*-*]} {
return 0
} else {
return 1
--
2.36.3
