Re: [PATCH] RISC-V: Add support for subword atomic loads/stores
On 6/13/24 12:58, Jeff Law wrote: On 6/12/24 6:10 PM, Patrick O'Neill wrote: Andrea Parri recently pointed out that we were emitting overly conservative fences for seq_cst atomic loads/stores. This adds support for the optimized fences specified in the PSABI: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/2092568f7896ceaa1ec0f02569b19eaa42cd51c9/riscv-atomic.adoc gcc/ChangeLog: * config/riscv/sync-rvwmo.md: Add support for subword fenced loads/stores. * config/riscv/sync-ztso.md: Ditto. * config/riscv/sync.md: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo/amo-table-a-6-load-1.c: Increase test coverage to include longs, shorts, chars, and bools. * gcc.target/riscv/amo/amo-table-a-6-load-2.c: Ditto. * gcc.target/riscv/amo/amo-table-a-6-load-3.c: Ditto. * gcc.target/riscv/amo/amo-table-a-6-store-1.c: Ditto. * gcc.target/riscv/amo/amo-table-a-6-store-2.c: Ditto. * gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-load-1.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-load-2.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-load-3.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-store-1.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-store-2.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-store-3.c: Ditto. OK jeff Committed with a fixup to the long case to match both ld/sd or lw/sw since that tripped up on rv32 targets. I resent the committed patch for the archiver. Patrick
Re: [PATCH] RISC-V: Add support for subword atomic loads/stores
On 6/12/24 6:10 PM, Patrick O'Neill wrote: Andrea Parri recently pointed out that we were emitting overly conservative fences for seq_cst atomic loads/stores. This adds support for the optimized fences specified in the PSABI: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/2092568f7896ceaa1ec0f02569b19eaa42cd51c9/riscv-atomic.adoc gcc/ChangeLog: * config/riscv/sync-rvwmo.md: Add support for subword fenced loads/stores. * config/riscv/sync-ztso.md: Ditto. * config/riscv/sync.md: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo/amo-table-a-6-load-1.c: Increase test coverage to include longs, shorts, chars, and bools. * gcc.target/riscv/amo/amo-table-a-6-load-2.c: Ditto. * gcc.target/riscv/amo/amo-table-a-6-load-3.c: Ditto. * gcc.target/riscv/amo/amo-table-a-6-store-1.c: Ditto. * gcc.target/riscv/amo/amo-table-a-6-store-2.c: Ditto. * gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-load-1.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-load-2.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-load-3.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-store-1.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-store-2.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-store-3.c: Ditto. OK jeff
Re: [PATCH] RISC-V: Add support for subword atomic loads/stores
On Wed, Jun 12, 2024 at 05:10:13PM -0700, Patrick O'Neill wrote: > Andrea Parri recently pointed out that we were emitting overly conservative > fences for seq_cst atomic loads/stores. This adds support for the optimized > fences specified in the PSABI: > https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/2092568f7896ceaa1ec0f02569b19eaa42cd51c9/riscv-atomic.adoc > > gcc/ChangeLog: > > * config/riscv/sync-rvwmo.md: Add support for subword fenced > loads/stores. > * config/riscv/sync-ztso.md: Ditto. > * config/riscv/sync.md: Ditto. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/amo/amo-table-a-6-load-1.c: Increase test coverage to > include longs, shorts, chars, and bools. > * gcc.target/riscv/amo/amo-table-a-6-load-2.c: Ditto. > * gcc.target/riscv/amo/amo-table-a-6-load-3.c: Ditto. > * gcc.target/riscv/amo/amo-table-a-6-store-1.c: Ditto. > * gcc.target/riscv/amo/amo-table-a-6-store-2.c: Ditto. > * gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c: Ditto. > * gcc.target/riscv/amo/amo-table-ztso-load-1.c: Ditto. > * gcc.target/riscv/amo/amo-table-ztso-load-2.c: Ditto. > * gcc.target/riscv/amo/amo-table-ztso-load-3.c: Ditto. > * gcc.target/riscv/amo/amo-table-ztso-store-1.c: Ditto. > * gcc.target/riscv/amo/amo-table-ztso-store-2.c: Ditto. > * gcc.target/riscv/amo/amo-table-ztso-store-3.c: Ditto. > > Signed-off-by: Patrick O'Neill Tested-by: Andrea Parri Andrea
[PATCH] RISC-V: Add support for subword atomic loads/stores
Andrea Parri recently pointed out that we were emitting overly conservative fences for seq_cst atomic loads/stores. This adds support for the optimized fences specified in the PSABI: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/2092568f7896ceaa1ec0f02569b19eaa42cd51c9/riscv-atomic.adoc gcc/ChangeLog: * config/riscv/sync-rvwmo.md: Add support for subword fenced loads/stores. * config/riscv/sync-ztso.md: Ditto. * config/riscv/sync.md: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo/amo-table-a-6-load-1.c: Increase test coverage to include longs, shorts, chars, and bools. * gcc.target/riscv/amo/amo-table-a-6-load-2.c: Ditto. * gcc.target/riscv/amo/amo-table-a-6-load-3.c: Ditto. * gcc.target/riscv/amo/amo-table-a-6-store-1.c: Ditto. * gcc.target/riscv/amo/amo-table-a-6-store-2.c: Ditto. * gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-load-1.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-load-2.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-load-3.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-store-1.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-store-2.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-store-3.c: Ditto. Signed-off-by: Patrick O'Neill --- Andrea Parri's comment: https://inbox.sourceware.org/gcc-patches/ZmeXGRF+zDktFqaY@andrea/ --- gcc/config/riscv/sync-rvwmo.md| 24 gcc/config/riscv/sync-ztso.md | 20 +++ gcc/config/riscv/sync.md | 8 +-- .../riscv/amo/amo-table-a-6-load-1.c | 48 +++- .../riscv/amo/amo-table-a-6-load-2.c | 52 - .../riscv/amo/amo-table-a-6-load-3.c | 56 ++- .../riscv/amo/amo-table-a-6-store-1.c | 48 +++- .../riscv/amo/amo-table-a-6-store-2.c | 52 - .../riscv/amo/amo-table-a-6-store-compat-3.c | 56 ++- .../riscv/amo/amo-table-ztso-load-1.c | 48 +++- .../riscv/amo/amo-table-ztso-load-2.c | 48 +++- .../riscv/amo/amo-table-ztso-load-3.c | 52 - .../riscv/amo/amo-table-ztso-store-1.c| 48 +++- .../riscv/amo/amo-table-ztso-store-2.c| 48 +++- .../riscv/amo/amo-table-ztso-store-3.c| 52 - 15 files changed, 610 insertions(+), 50 deletions(-) diff --git a/gcc/config/riscv/sync-rvwmo.md b/gcc/config/riscv/sync-rvwmo.md index e639a1e2392..5db94c8c27f 100644 --- a/gcc/config/riscv/sync-rvwmo.md +++ b/gcc/config/riscv/sync-rvwmo.md @@ -47,9 +47,9 @@ ;; Atomic memory operations. (define_insn "atomic_load_rvwmo" - [(set (match_operand:GPR 0 "register_operand" "=r") - (unspec_volatile:GPR - [(match_operand:GPR 1 "memory_operand" "A") + [(set (match_operand:ANYI 0 "register_operand" "=r") + (unspec_volatile:ANYI + [(match_operand:ANYI 1 "memory_operand" "A") (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_ATOMIC_LOAD))] "!TARGET_ZTSO" @@ -59,13 +59,13 @@ if (model == MEMMODEL_SEQ_CST) return "fence\trw,rw\;" -"l\t%0,%1\;" +"\t%0,%1\;" "fence\tr,rw"; if (model == MEMMODEL_ACQUIRE) - return "l\t%0,%1\;" + return "\t%0,%1\;" "fence\tr,rw"; else - return "l\t%0,%1"; + return "\t%0,%1"; } [(set_attr "type" "multi") (set (attr "length") (const_int 12))]) @@ -73,9 +73,9 @@ ;; Implement atomic stores with conservative fences. ;; This allows us to be compatible with the ISA manual Table A.6 and Table A.7. (define_insn "atomic_store_rvwmo" - [(set (match_operand:GPR 0 "memory_operand" "=A") - (unspec_volatile:GPR - [(match_operand:GPR 1 "reg_or_0_operand" "rJ") + [(set (match_operand:ANYI 0 "memory_operand" "=A") + (unspec_volatile:ANYI + [(match_operand:ANYI 1 "reg_or_0_operand" "rJ") (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_ATOMIC_STORE))] "!TARGET_ZTSO" @@ -85,13 +85,13 @@ if (model == MEMMODEL_SEQ_CST) return "fence\trw,w\;" -"s\t%z1,%0\;" +"\t%z1,%0\;" "fence\trw,rw"; if (model == MEMMODEL_RELEASE) return "fence\trw,w\;" -"s\t%z1,%0"; +"\t%z1,%0"; else - return "s\t%z1,%0"; + return "\t%z1,%0"; } [(set_attr "type" "multi") (set (attr "length") (const_int 12))]) diff --git a/gcc/config/riscv/sync-ztso.md b/gcc/config/riscv/sync-ztso.md index 0a866d2906b..f99a21b45ca 100644 --- a/gcc/config/riscv/sync-ztso.md +++ b/gcc/config/riscv/sync-ztso.md @@ -41,9 +41,9 @@ ;; Atomic memory operations. (define_insn "atomic_load_ztso" - [(set (match_operand:GPR 0 "register_operand" "=r") - (unspec_vol
