[PATCH] RISC-V: Add vector fmin/fmax expanders.
Hi, this patch adds expanders for fmin and fmax and the associated cond and reduc ones. As per RISC-V V spec 1.0 vfmin/vfmax are IEEE 754-2008 compliant so that should be ok. Regards Robin gcc/ChangeLog: * config/riscv/autovec.md (3): fmax/fmin expanders. (cond_): Ditto. (cond_len_): Ditto. (reduc_fmax_scal_): Ditto. (reduc_fmin_scal_): Ditto. * config/riscv/riscv-v.cc (needs_fp_rounding): Add fmin/fmax. * config/riscv/vector-iterators.md (fmin): New UNSPEC. (UNSPEC_VFMIN): Ditto. * config/riscv/vector.md (@pred_): Add UNSPEC insn patterns. (@pred__scalar): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c: Remove -ffast-math. * gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/fmax-1.c: New test. * gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c: New test. * gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c: New test. * gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c: New test. * gcc.target/riscv/rvv/autovec/binop/fmin-1.c: New test. * gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c: New test. * gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c: New test. * gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c: New test. * gcc.target/riscv/rvv/autovec/reduc/reduc-10.c: New test. * gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c: New test. * gcc.target/riscv/rvv/autovec/reduc/reduc_run_zvfh-10.c: New test. * gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c: New test. --- gcc/config/riscv/autovec.md | 72 +++ gcc/config/riscv/riscv-v.cc | 2 + gcc/config/riscv/vector-iterators.md | 8 +++ gcc/config/riscv/vector.md| 43 +++ .../riscv/rvv/autovec/binop/fmax-1.c | 24 +++ .../riscv/rvv/autovec/binop/fmax_run-1.c | 47 .../riscv/rvv/autovec/binop/fmax_zvfh-1.c | 23 ++ .../riscv/rvv/autovec/binop/fmax_zvfh_run-1.c | 48 + .../riscv/rvv/autovec/binop/fmin-1.c | 10 +++ .../riscv/rvv/autovec/binop/fmin_run-1.c | 5 ++ .../riscv/rvv/autovec/binop/fmin_zvfh-1.c | 10 +++ .../riscv/rvv/autovec/binop/fmin_zvfh_run-1.c | 5 ++ .../riscv/rvv/autovec/cond/cond_fmax-1.c | 6 +- .../riscv/rvv/autovec/cond/cond_fmax-2.c | 3 +- .../riscv/rvv/autovec/cond/cond_fmax-3.c | 6 +- .../riscv/rvv/autovec/cond/cond_fmax-4.c | 6 +- .../riscv/rvv/autovec/cond/cond_fmax_run-1.c | 3 +- .../riscv/rvv/autovec/cond/cond_fmax_run-2.c | 3 +- .../riscv/rvv/autovec/cond/cond_fmax_run-3.c | 3 +- .../riscv/rvv/autovec/co
Re: [PATCH] RISC-V: Add vector fmin/fmax expanders.
On Mon, 30 Oct 2023, Robin Dapp wrote: > Hi, > > this patch adds expanders for fmin and fmax and the associated > cond and reduc ones. As per RISC-V V spec 1.0 vfmin/vfmax are > IEEE 754-2008 compliant so that should be ok. Aren't they actually the IEEE 754-2019 operations (with different signaling NaN semantics; C functions such as fmaximum in C23), not the IEEE 754-2008 operations (C functions such as fmax)? V spec 1.0 says "The vector floating-point vfmin and vfmax instructions have the same behavior as the corresponding scalar floating-point instructions in version 2.2 of the RISC-V F/D/Q extension.". And version 2.2 of F/D/Q (which is *not* version 2.2 of the instruction set, it's later than that) changed the scalar instructions to be the IEEE 754-2019 operations (thus, the !HONOR_SNANS checks in the back end). -- Joseph S. Myers jos...@codesourcery.com
Re: [PATCH] RISC-V: Add vector fmin/fmax expanders.
> Aren't they actually the IEEE 754-2019 operations (with different > signaling NaN semantics; C functions such as fmaximum in C23), not the > IEEE 754-2008 operations (C functions such as fmax)? V spec 1.0 says "The > vector floating-point vfmin and vfmax instructions have the same behavior > as the corresponding scalar floating-point instructions in version 2.2 of > the RISC-V F/D/Q extension.". And version 2.2 of F/D/Q (which is *not* > version 2.2 of the instruction set, it's later than that) changed the Oh, thanks for catching this - I indeed incorrectly assumed this refers to version 2.2 of the RISC-V spec (which contains F/D, .. of version 2.0). Too bad, it appeared too convenient. Then I need to add the same !HONOR_SNANS to all the expanders as well as the tests. Regards Robin
Re: [PATCH] RISC-V: Add vector fmin/fmax expanders.
Thanks, going to commit the attached. Regards Robin This patch adds expanders for fmin and fmax. As per RISC-V V Spec 1.0 vfmin/vfmax are IEEE 754-2019 compliant which differs from IEEE 754-2008 that fmin/fmax require (particularly in the signaling-NaN handling). Therefore the pattern conditions include a !HONOR_SNANS. gcc/ChangeLog: * config/riscv/autovec.md (3): fmax/fmin expanders. (cond_): Ditto. (cond_len_): Ditto. (reduc_fmax_scal_): Ditto. (reduc_fmin_scal_): Ditto. * config/riscv/riscv-v.cc (needs_fp_rounding): Add fmin/fmax. * config/riscv/vector-iterators.md (fmin): New UNSPEC. (UNSPEC_VFMIN): Ditto. * config/riscv/vector.md (@pred_): Add UNSPEC insn patterns. (@pred__scalar): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c: Remove -ffast-math. * gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/fmax-1.c: New test. * gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c: New test. * gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c: New test. * gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c: New test. * gcc.target/riscv/rvv/autovec/binop/fmin-1.c: New test. * gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c: New test. * gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c: New test. * gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c: New test. * gcc.target/riscv/rvv/autovec/reduc/reduc-10.c: New test. * gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c: New test. * gcc.target/riscv/rvv/autovec/reduc/reduc_run_zvfh-10.c: New test. * gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c: New test. --- gcc/config/riscv/autovec.md | 72 +++ gcc/config/riscv/riscv-v.cc | 2 + gcc/config/riscv/vector-iterators.md | 8 +++ gcc/config/riscv/vector.md| 43 +++ .../riscv/rvv/autovec/binop/fmax-1.c | 24 +++ .../riscv/rvv/autovec/binop/fmax_run-1.c | 47 .../riscv/rvv/autovec/binop/fmax_zvfh-1.c | 23 ++ .../riscv/rvv/autovec/binop/fmax_zvfh_run-1.c | 48 + .../riscv/rvv/autovec/binop/fmin-1.c | 10 +++ .../riscv/rvv/autovec/binop/fmin_run-1.c | 5 ++ .../riscv/rvv/autovec/binop/fmin_zvfh-1.c | 10 +++ .../riscv/rvv/autovec/binop/fmin_zvfh_run-1.c | 5 ++ .../riscv/rvv/autovec/cond/cond_fmax-1.c | 6 +- .../riscv/rvv/autovec/cond/cond_fmax-2.c | 3 +- .../riscv/rvv/autovec/cond/cond_fmax-3.c | 6 +- .../riscv/rvv/autovec/cond/cond_fmax-4.c | 6 +- .../riscv/rvv/autovec/cond/cond_fmax_run-1.c | 3 +- ..
Re: Re: [PATCH] RISC-V: Add vector fmin/fmax expanders.
LGTM as long as you add HONOR_SNANS juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-10-31 03:26 To: Joseph Myers CC: rdapp.gcc; gcc-patches; palmer; Kito Cheng; jeffreyalaw; juzhe.zh...@rivai.ai Subject: Re: [PATCH] RISC-V: Add vector fmin/fmax expanders. > Aren't they actually the IEEE 754-2019 operations (with different > signaling NaN semantics; C functions such as fmaximum in C23), not the > IEEE 754-2008 operations (C functions such as fmax)? V spec 1.0 says "The > vector floating-point vfmin and vfmax instructions have the same behavior > as the corresponding scalar floating-point instructions in version 2.2 of > the RISC-V F/D/Q extension.". And version 2.2 of F/D/Q (which is *not* > version 2.2 of the instruction set, it's later than that) changed the Oh, thanks for catching this - I indeed incorrectly assumed this refers to version 2.2 of the RISC-V spec (which contains F/D, .. of version 2.0). Too bad, it appeared too convenient. Then I need to add the same !HONOR_SNANS to all the expanders as well as the tests. Regards Robin
