From: Pan Li
We reverted below patch for wv insn overlap, add the related wv
insn test and mark it as xfail. And we will remove the xfail
after we support the register overlap in GCC-15.
7e854b58084 RISC-V: Support highest overlap for wv instructions
The below test suites are passed.
* The rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-11.c: Xfail csr check.
* gcc.target/riscv/rvv/base/pr112431-39.c: New test.
* gcc.target/riscv/rvv/base/pr112431-40.c: New test.
* gcc.target/riscv/rvv/base/pr112431-41.c: New test.
Signed-off-by: Pan Li
---
.../costmodel/riscv/rvv/dynamic-lmul8-11.c| 2 +-
.../gcc.target/riscv/rvv/base/pr112431-39.c | 158 ++
.../gcc.target/riscv/rvv/base/pr112431-40.c | 94 +++
.../gcc.target/riscv/rvv/base/pr112431-41.c | 62 +++
4 files changed, 315 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-39.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-40.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-41.c
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-11.c
b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-11.c
index c9e28251225..5a39f04b140 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-11.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-11.c
@@ -40,7 +40,7 @@ void foo2 (int64_t *__restrict a,
}
/* { dg-final { scan-assembler {e64,m8} } } */
-/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
/* { dg-final { scan-tree-dump-not "Preferring smaller LMUL loop because it
has unexpected spills" "vect" } } */
/* { dg-final { scan-tree-dump-times "Maximum lmul = 8" 1 "vect" } } */
/* { dg-final { scan-tree-dump-times "Maximum lmul = 4" 1 "vect" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-39.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-39.c
new file mode 100644
index 000..770b5411666
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-39.c
@@ -0,0 +1,158 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+void
+foo (void *in, void *out, int n)
+{
+ for (int i = 0; i < n; i++)
+{
+ asm volatile("nop" ::: "memory");
+ vint16m2_t v0 = __riscv_vle16_v_i16m2 (in, 4);in+=100;
+ v0 = __riscv_vwsub_wv_i16m2_tu (v0, v0,
__riscv_vreinterpret_v_i16m1_i8m1 (__riscv_vget_v_i16m2_i16m1 (v0, 1)), 4);
+ asm volatile("nop" ::: "memory");
+ vint16m2_t v1 = __riscv_vle16_v_i16m2 (in, 4);in+=100;
+ v1 = __riscv_vwsub_wv_i16m2_tu (v1, v1,
__riscv_vreinterpret_v_i16m1_i8m1 (__riscv_vget_v_i16m2_i16m1 (v1, 1)), 4);
+ asm volatile("nop" ::: "memory");
+ vint16m2_t v2 = __riscv_vle16_v_i16m2 (in, 4);in+=100;
+ v2 = __riscv_vwsub_wv_i16m2_tu (v2, v2,
__riscv_vreinterpret_v_i16m1_i8m1 (__riscv_vget_v_i16m2_i16m1 (v2, 1)), 4);
+ asm volatile("nop" ::: "memory");
+ vint16m2_t v3 = __riscv_vle16_v_i16m2 (in, 4);in+=100;
+ v3 = __riscv_vwsub_wv_i16m2_tu (v3, v3,
__riscv_vreinterpret_v_i16m1_i8m1 (__riscv_vget_v_i16m2_i16m1 (v3, 1)), 4);
+ asm volatile("nop" ::: "memory");
+ vint16m2_t v4 = __riscv_vle16_v_i16m2 (in, 4);in+=100;
+ v4 = __riscv_vwsub_wv_i16m2_tu (v4, v4,
__riscv_vreinterpret_v_i16m1_i8m1 (__riscv_vget_v_i16m2_i16m1 (v4, 1)), 4);
+ asm volatile("nop" ::: "memory");
+ vint16m2_t v5 = __riscv_vle16_v_i16m2 (in, 4);in+=100;
+ v5 = __riscv_vwsub_wv_i16m2_tu (v5, v5,
__riscv_vreinterpret_v_i16m1_i8m1 (__riscv_vget_v_i16m2_i16m1 (v5, 1)), 4);
+ asm volatile("nop" ::: "memory");
+ vint16m2_t v6 = __riscv_vle16_v_i16m2 (in, 4);in+=100;
+ v6 = __riscv_vwsub_wv_i16m2_tu (v6, v6,
__riscv_vreinterpret_v_i16m1_i8m1 (__riscv_vget_v_i16m2_i16m1 (v6, 1)), 4);
+ asm volatile("nop" ::: "memory");
+ vint16m2_t v7 = __riscv_vle16_v_i16m2 (in, 4);in+=100;
+ v7 = __riscv_vwsub_wv_i16m2_tu (v7, v7,
__riscv_vreinterpret_v_i16m1_i8m1 (__riscv_vget_v_i16m2_i16m1 (v7, 1)), 4);
+ asm volatile("nop" ::: "memory");
+ vint16m2_t v8 = __riscv_vle16_v_i16m2 (in, 4);in+=100;
+ v8 = __riscv_vwsub_wv_i16m2_tu (v8, v8,
__riscv_vreinterpret_v_i16m1_i8m1 (__riscv_vget_v_i16m2_i16m1 (v8, 1)), 4);
+ asm volatile("nop" ::: "memory");
+ vint16m2_t v9 = __riscv_vle16_v_i16m2 (in, 4);in+=100;
+ v9 = __riscv_vwsub_wv_i16m2_tu (v9, v9,
__riscv_vreinterpret_v_i16m1_i8m1 (__riscv_vget_v_i16m2_i16m1 (v9, 1)), 4);
+ asm volatile("nop" ::: "memory");
+ vint16m2_t v10 = __riscv_vle16_v_i16m2 (in, 4);in+=100;
+ v10 = __riscv_vwsub_wv_i16m2_tu (v10, v10,
__riscv_vreinterpret_v_i16m1_i8m1 (__riscv_vget_v_i16m2_i16m1 (v10, 1)), 4);
+ asm volatile("nop" ::: "memory");
+
