Re: [PATCH] RISC-V: Fix RVV related testsuite

[Andreas Schwab]

Perhaps rvv.exp should add -I. so that the wrapper is found regardless?

-- 
Andreas Schwab, sch...@linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510  2552 DF73 E780 A9DA AEC1
"And now for something completely different."

[PATCH] RISC-V: Fix RVV related testsuite

[Kito Cheng]

Use wrapper of riscv_vector.h for RVV related testcases,
more detail see 
https://gcc.gnu.org/pipermail/gcc-patches/2022-October/603140.html

gcc/testsuite/ChangeLog:

* gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c: Use double quotes to
include riscv_vector.h rather than angle brackets.
* gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c: Ditto.
* gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c: Ditto.
* gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c: Ditto.
* gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c: Ditto.
* gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c: Ditto.
* gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c: Ditto.
* gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c: Ditto.
* gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c: Ditto.
* gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c: Ditto.
* gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c: Ditto.
* gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c: Ditto.
* gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c: Ditto.
* gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c: Ditto.
* gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c: Ditto.
* gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c: Ditto.
---
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c   | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c | 2 +-
 16 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c
index 6a235e308f9..cfc565b8922 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include 
+#include "riscv_vector.h"
 
 /*
 ** mov1:
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c
index 10aa8297c30..419f19d0184 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include  
+#include "riscv_vector.h" 
 
 /*
 ** mov1:
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c
index f8da5bb6b93..1bb159c7099 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include  
+#include "riscv_vector.h" 
 
 /*
 ** mov1:
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c
index 5b8ce40b62d..7886886e2f5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include  
+#include "riscv_vector.h" 
 
 /*
 ** mov14:
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c
index 8c630f3bedb..9515e07eca1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 
-#include  
+#include "riscv_vector.h" 
 
 void mov1 (int8_t *in, int8_t *out) 
 { 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c
index b9bdd515747..301607a2906 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv3