Re: [PATCH] RISC-V: Keep vlmax vector operators in simple form until split1 pass

[Lehua Ding]

Committed, thanks Kito.

--
Best,
Lehua

Re: [PATCH] RISC-V: Keep vlmax vector operators in simple form until split1 pass

[Kito Cheng via Gcc-patches]

Thanks for explaining, LGTM :)


On Mon, Sep 4, 2023 at 11:39 PM Lehua Ding  wrote:
>
> Hi Kito,
>
> > Can those intermediate patterns be used for intrinsic? I would prefer
> > to keep those stuff *IF* possible used for intrinsics.
>
> I think we don't need those patterns for intrinisc. First, the deleted
> pattern does not directly correspond to intrinisc. Second, if you want
> to use these patterns to optimize the following intrinisc program (e.g.
> combine to a single vwadd.vv instruction), we'd better fold them
> directly into the internal function of autovec in Gimple IR.
>
>vint32m1_t foo(vint16mf2_t va1, vint16mf2_t vb1) {
>  vint32m1_t va2 = __riscv_vsext_vf2_i32m1(va1,
> __riscv_vsetvlmax_e32m1());
>  vint32m1_t vb2 = __riscv_vsext_vf2_i32m1(vb1,
> __riscv_vsetvlmax_e32m1());
>  vint32m1_t vc = __riscv_vadd_vv_i32m1(va2, vb2,
> __riscv_vsetvlmax_e32m1());
>  return vc;
>}
> --
> Best,
> Lehua
>
>

Re: [PATCH] RISC-V: Keep vlmax vector operators in simple form until split1 pass

[Lehua Ding]

Hi Kito,


Can those intermediate patterns be used for intrinsic? I would prefer
to keep those stuff *IF* possible used for intrinsics.


I think we don't need those patterns for intrinisc. First, the deleted 
pattern does not directly correspond to intrinisc. Second, if you want 
to use these patterns to optimize the following intrinisc program (e.g. 
combine to a single vwadd.vv instruction), we'd better fold them 
directly into the internal function of autovec in Gimple IR.


  vint32m1_t foo(vint16mf2_t va1, vint16mf2_t vb1) {
vint32m1_t va2 = __riscv_vsext_vf2_i32m1(va1, 
__riscv_vsetvlmax_e32m1());
vint32m1_t vb2 = __riscv_vsext_vf2_i32m1(vb1, 
__riscv_vsetvlmax_e32m1());
vint32m1_t vc = __riscv_vadd_vv_i32m1(va2, vb2, 
__riscv_vsetvlmax_e32m1());

return vc;
  }
--
Best,
Lehua

Re: [PATCH] RISC-V: Keep vlmax vector operators in simple form until split1 pass

[Kito Cheng via Gcc-patches]

Can those intermediate patterns be used for intrinsic? I would prefer
to keep those stuff *IF* possible used for intrinsics.

On Mon, Sep 4, 2023 at 7:14 PM Lehua Ding  wrote:
>
> This patch keep vlmax vector pattern in simple before split1 pass which
> will allow more optimization (e.g. combine) before split1 pass.
> This patch changes the vlmax pattern in autovec.md to define_insn_and_split
> as much as possible and clean up some combine patterns that are no longer 
> needed.
> This patch also fixed PR111232 bug which was caused by a combined failed.
>
> PR target/111232
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md 
> (@pred_single_widen_mul):
> Delete.
> (*pred_widen_mulsu): Delete.
> (*pred_single_widen_mul): Delete.
> (*dual_widen_):
> Add new combine patterns.
> (*single_widen_sub): Ditto.
> (*single_widen_add): Ditto.
> (*single_widen_mult): Ditto.
> (*dual_widen_mulsu): Ditto.
> (*dual_widen_mulus): Ditto.
> (*dual_widen_): Ditto.
> (*single_widen_add): Ditto.
> (*single_widen_sub): Ditto.
> (*single_widen_mult): Ditto.
> * config/riscv/autovec.md (3):
> Change define_expand to define_insn_and_split.
> (2): Ditto.
> (abs2): Ditto.
> (smul3_highpart): Ditto.
> (umul3_highpart): Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/widen/widen-4.c: Add more testcases.
> * gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c: Ditto.
> * gcc.target/riscv/rvv/autovec/pr111232.c: New test.
>
> ---
>  gcc/config/riscv/autovec-opt.md   | 294 --
>  gcc/config/riscv/autovec.md   |  82 +++--
>  .../gcc.target/riscv/rvv/autovec/pr111232.c   |  18 ++
>  .../riscv/rvv/autovec/widen/widen-4.c |   7 +-
>  .../rvv/autovec/widen/widen-complicate-4.c|  11 +-
>  5 files changed, 276 insertions(+), 136 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111232.c
>
> diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
> index d9863c76654..3aaee54f02a 100644
> --- a/gcc/config/riscv/autovec-opt.md
> +++ b/gcc/config/riscv/autovec-opt.md
> @@ -18,67 +18,6 @@
>  ;; along with GCC; see the file COPYING3.  If not see
>  ;; .
>
> -;; We don't have vwmul.wv instruction like vwadd.wv in RVV.
> -;; This pattern is an intermediate RTL IR as a pseudo vwmul.wv to enhance
> -;; optimization of instructions combine.
> -(define_insn_and_split "@pred_single_widen_mul"
> -  [(set (match_operand:VWEXTI 0 "register_operand"  
> "=&vr,&vr")
> -   (if_then_else:VWEXTI
> - (unspec:
> -   [(match_operand: 1 "vector_mask_operand"   
> "vmWc1,vmWc1")
> -(match_operand 5 "vector_length_operand"  "   rK,   
> rK")
> -(match_operand 6 "const_int_operand"  "i,
> i")
> -(match_operand 7 "const_int_operand"  "i,
> i")
> -(match_operand 8 "const_int_operand"  "i,
> i")
> -(reg:SI VL_REGNUM)
> -(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> - (mult:VWEXTI
> -   (any_extend:VWEXTI
> - (match_operand: 4 "register_operand" "   vr,   
> vr"))
> -   (match_operand:VWEXTI 3 "register_operand" "   vr,   
> vr"))
> - (match_operand:VWEXTI 2 "vector_merge_operand"   "   vu,
> 0")))]
> -  "TARGET_VECTOR && can_create_pseudo_p ()"
> -  "#"
> -  "&& 1"
> -  [(const_int 0)]
> -  {
> -insn_code icode = code_for_pred_vf2 (, mode);
> -rtx tmp = gen_reg_rtx (mode);
> -rtx ops[] = {tmp, operands[4]};
> -riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, ops);
> -
> -emit_insn (gen_pred (MULT, mode, operands[0], operands[1], 
> operands[2],
> -operands[3], tmp, operands[5], operands[6],
> -operands[7], operands[8]));
> -DONE;
> -  }
> -  [(set_attr "type" "viwmul")
> -   (set_attr "mode" "")])
> -
> -;; This pattern it to enchance the instruction combine optimizations for 
> complicate
> -;; sign and unsigned widening multiplication operations.
> -(define_insn "*pred_widen_mulsu"
> -  [(set (match_operand:VWEXTI 0 "register_operand"  
> "=&vr,&vr")
> -   (if_then_else:VWEXTI
> - (unspec:
> -   [(match_operand: 1 "vector_mask_operand"   
> "vmWc1,vmWc1")
> -(match_operand 5 "vector_length_operand"  "   rK,   
> rK")
> -(match_operand 6 "const_int_operand"  "i,
> i")
> -(match_operand 7 "const_int_operand"  "i,
> i")
> -(match_operand 8 "const_int_operand"  "i,
> i")
> -(reg:SI VL_REGN

[PATCH] RISC-V: Keep vlmax vector operators in simple form until split1 pass

[Lehua Ding]

This patch keep vlmax vector pattern in simple before split1 pass which
will allow more optimization (e.g. combine) before split1 pass.
This patch changes the vlmax pattern in autovec.md to define_insn_and_split
as much as possible and clean up some combine patterns that are no longer 
needed.
This patch also fixed PR111232 bug which was caused by a combined failed.

PR target/111232

gcc/ChangeLog:

* config/riscv/autovec-opt.md 
(@pred_single_widen_mul):
Delete.
(*pred_widen_mulsu): Delete.
(*pred_single_widen_mul): Delete.
(*dual_widen_):
Add new combine patterns.
(*single_widen_sub): Ditto.
(*single_widen_add): Ditto.
(*single_widen_mult): Ditto.
(*dual_widen_mulsu): Ditto.
(*dual_widen_mulus): Ditto.
(*dual_widen_): Ditto.
(*single_widen_add): Ditto.
(*single_widen_sub): Ditto.
(*single_widen_mult): Ditto.
* config/riscv/autovec.md (3):
Change define_expand to define_insn_and_split.
(2): Ditto.
(abs2): Ditto.
(smul3_highpart): Ditto.
(umul3_highpart): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/widen/widen-4.c: Add more testcases.
* gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/pr111232.c: New test.

---
 gcc/config/riscv/autovec-opt.md   | 294 --
 gcc/config/riscv/autovec.md   |  82 +++--
 .../gcc.target/riscv/rvv/autovec/pr111232.c   |  18 ++
 .../riscv/rvv/autovec/widen/widen-4.c |   7 +-
 .../rvv/autovec/widen/widen-complicate-4.c|  11 +-
 5 files changed, 276 insertions(+), 136 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111232.c

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index d9863c76654..3aaee54f02a 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -18,67 +18,6 @@
 ;; along with GCC; see the file COPYING3.  If not see
 ;; .
 
-;; We don't have vwmul.wv instruction like vwadd.wv in RVV.
-;; This pattern is an intermediate RTL IR as a pseudo vwmul.wv to enhance
-;; optimization of instructions combine.
-(define_insn_and_split "@pred_single_widen_mul"
-  [(set (match_operand:VWEXTI 0 "register_operand"  "=&vr,&vr")
-   (if_then_else:VWEXTI
- (unspec:
-   [(match_operand: 1 "vector_mask_operand"   
"vmWc1,vmWc1")
-(match_operand 5 "vector_length_operand"  "   rK,   
rK")
-(match_operand 6 "const_int_operand"  "i,
i")
-(match_operand 7 "const_int_operand"  "i,
i")
-(match_operand 8 "const_int_operand"  "i,
i")
-(reg:SI VL_REGNUM)
-(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (mult:VWEXTI
-   (any_extend:VWEXTI
- (match_operand: 4 "register_operand" "   vr,   
vr"))
-   (match_operand:VWEXTI 3 "register_operand" "   vr,   
vr"))
- (match_operand:VWEXTI 2 "vector_merge_operand"   "   vu,
0")))]
-  "TARGET_VECTOR && can_create_pseudo_p ()"
-  "#"
-  "&& 1"
-  [(const_int 0)]
-  {
-insn_code icode = code_for_pred_vf2 (, mode);
-rtx tmp = gen_reg_rtx (mode);
-rtx ops[] = {tmp, operands[4]};
-riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, ops);
-
-emit_insn (gen_pred (MULT, mode, operands[0], operands[1], 
operands[2],
-operands[3], tmp, operands[5], operands[6],
-operands[7], operands[8]));
-DONE;
-  }
-  [(set_attr "type" "viwmul")
-   (set_attr "mode" "")])
-
-;; This pattern it to enchance the instruction combine optimizations for 
complicate
-;; sign and unsigned widening multiplication operations.
-(define_insn "*pred_widen_mulsu"
-  [(set (match_operand:VWEXTI 0 "register_operand"  "=&vr,&vr")
-   (if_then_else:VWEXTI
- (unspec:
-   [(match_operand: 1 "vector_mask_operand"   
"vmWc1,vmWc1")
-(match_operand 5 "vector_length_operand"  "   rK,   
rK")
-(match_operand 6 "const_int_operand"  "i,
i")
-(match_operand 7 "const_int_operand"  "i,
i")
-(match_operand 8 "const_int_operand"  "i,
i")
-(reg:SI VL_REGNUM)
-(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (mult:VWEXTI
-   (zero_extend:VWEXTI
- (match_operand: 4 "register_operand" "   vr,   
vr"))
-   (sign_extend:VWEXTI
- (match_operand: 3 "register_operand" "   vr,   
vr")))
- (match_operand:VWEXTI 2 "vector_merge_operand"   "   vu,
0")))]
-  "TARGET_VECTOR"
-  "vwmulsu.vv\t%0,%3,%4%p1"