RE: [PATCH] RISC-V: Make sure we get VL REG operand for VLMAX vsetvl

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Kito Cheng via Gcc-patches
Sent: Wednesday, August 30, 2023 10:57 AM
To: Juzhe-Zhong 
Cc: gcc-patches@gcc.gnu.org; kito.ch...@sifive.com
Subject: Re: [PATCH] RISC-V: Make sure we get VL REG operand for VLMAX vsetvl

Lgtm

Juzhe-Zhong 於 2023年8月30日 週三，10:22寫道：

> Fix ICE in "vect" testsuite:
>
> FAIL: gcc.dg/vect/pr64495.c (internal compiler error: in df_uses_record,
> at df-scan.cc:2958)
> FAIL: gcc.dg/vect/pr64495.c (test for excess errors
>
> After this patch, all current found VSETVL PASS related bugs in "vect" are
> fixed.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc
> (vector_insn_info::get_avl_or_vl_reg): Fix bug.
>
> ---
>  gcc/config/riscv/riscv-vsetvl.cc | 16 
>  1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc
> b/gcc/config/riscv/riscv-vsetvl.cc
> index 73d672b083b..1386d9250ca 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -2300,18 +2300,26 @@ vector_insn_info::get_avl_or_vl_reg (void) const
>if (!vlmax_avl_p (get_avl ()))
>  return get_avl ();
>
> -  if (has_vl_op (get_insn ()->rtl ()) || vsetvl_insn_p (get_insn ()->rtl
> ()))
> -return ::get_vl (get_insn ()->rtl ());
> -
>if (get_avl_source ())
>  return get_avl_reg_rtx ();
>
> +  rtx_insn *rinsn = get_insn ()->rtl ();
> +  if (has_vl_op (rinsn) || vsetvl_insn_p (rinsn))
> +{
> +  rtx vl = ::get_vl (rinsn);
> +  /* For VLMAX, we should make sure we get the
> +REG to emit 'vsetvl VL,zero' since the 'VL'
> +should be the REG according to RVV ISA.  */
> +  if (REG_P (vl))
> +   return vl;
> +}
> +
>/* A DIRTY (polluted EMPTY) block if:
> - get_insn is scalar move (no AVL or VL operand).
> - get_avl_source is null (no def in the current DIRTY block).
>   Then we trace the previous insn which must be the insn
>   already inserted in Phase 2 to get the VL operand for VLMAX.  */
> -  rtx_insn *prev_rinsn = PREV_INSN (get_insn ()->rtl ());
> +  rtx_insn *prev_rinsn = PREV_INSN (rinsn);
>gcc_assert (prev_rinsn && vsetvl_insn_p (prev_rinsn));
>return ::get_vl (prev_rinsn);
>  }
> --
> 2.36.3
>
>

Re: [PATCH] RISC-V: Make sure we get VL REG operand for VLMAX vsetvl

[Kito Cheng via Gcc-patches]

Lgtm

Juzhe-Zhong 於 2023年8月30日 週三，10:22寫道：

> Fix ICE in "vect" testsuite:
>
> FAIL: gcc.dg/vect/pr64495.c (internal compiler error: in df_uses_record,
> at df-scan.cc:2958)
> FAIL: gcc.dg/vect/pr64495.c (test for excess errors
>
> After this patch, all current found VSETVL PASS related bugs in "vect" are
> fixed.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc
> (vector_insn_info::get_avl_or_vl_reg): Fix bug.
>
> ---
>  gcc/config/riscv/riscv-vsetvl.cc | 16 
>  1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc
> b/gcc/config/riscv/riscv-vsetvl.cc
> index 73d672b083b..1386d9250ca 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -2300,18 +2300,26 @@ vector_insn_info::get_avl_or_vl_reg (void) const
>if (!vlmax_avl_p (get_avl ()))
>  return get_avl ();
>
> -  if (has_vl_op (get_insn ()->rtl ()) || vsetvl_insn_p (get_insn ()->rtl
> ()))
> -return ::get_vl (get_insn ()->rtl ());
> -
>if (get_avl_source ())
>  return get_avl_reg_rtx ();
>
> +  rtx_insn *rinsn = get_insn ()->rtl ();
> +  if (has_vl_op (rinsn) || vsetvl_insn_p (rinsn))
> +{
> +  rtx vl = ::get_vl (rinsn);
> +  /* For VLMAX, we should make sure we get the
> +REG to emit 'vsetvl VL,zero' since the 'VL'
> +should be the REG according to RVV ISA.  */
> +  if (REG_P (vl))
> +   return vl;
> +}
> +
>/* A DIRTY (polluted EMPTY) block if:
> - get_insn is scalar move (no AVL or VL operand).
> - get_avl_source is null (no def in the current DIRTY block).
>   Then we trace the previous insn which must be the insn
>   already inserted in Phase 2 to get the VL operand for VLMAX.  */
> -  rtx_insn *prev_rinsn = PREV_INSN (get_insn ()->rtl ());
> +  rtx_insn *prev_rinsn = PREV_INSN (rinsn);
>gcc_assert (prev_rinsn && vsetvl_insn_p (prev_rinsn));
>return ::get_vl (prev_rinsn);
>  }
> --
> 2.36.3
>
>

[PATCH] RISC-V: Make sure we get VL REG operand for VLMAX vsetvl

[Juzhe-Zhong]

Fix ICE in "vect" testsuite:

FAIL: gcc.dg/vect/pr64495.c (internal compiler error: in df_uses_record, at 
df-scan.cc:2958)
FAIL: gcc.dg/vect/pr64495.c (test for excess errors

After this patch, all current found VSETVL PASS related bugs in "vect" are 
fixed.

gcc/ChangeLog:

* config/riscv/riscv-vsetvl.cc (vector_insn_info::get_avl_or_vl_reg): 
Fix bug.

---
 gcc/config/riscv/riscv-vsetvl.cc | 16 
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 73d672b083b..1386d9250ca 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -2300,18 +2300,26 @@ vector_insn_info::get_avl_or_vl_reg (void) const
   if (!vlmax_avl_p (get_avl ()))
 return get_avl ();
 
-  if (has_vl_op (get_insn ()->rtl ()) || vsetvl_insn_p (get_insn ()->rtl ()))
-return ::get_vl (get_insn ()->rtl ());
-
   if (get_avl_source ())
 return get_avl_reg_rtx ();
 
+  rtx_insn *rinsn = get_insn ()->rtl ();
+  if (has_vl_op (rinsn) || vsetvl_insn_p (rinsn))
+{
+  rtx vl = ::get_vl (rinsn);
+  /* For VLMAX, we should make sure we get the
+REG to emit 'vsetvl VL,zero' since the 'VL'
+should be the REG according to RVV ISA.  */
+  if (REG_P (vl))
+   return vl;
+}
+
   /* A DIRTY (polluted EMPTY) block if:
- get_insn is scalar move (no AVL or VL operand).
- get_avl_source is null (no def in the current DIRTY block).
  Then we trace the previous insn which must be the insn
  already inserted in Phase 2 to get the VL operand for VLMAX.  */
-  rtx_insn *prev_rinsn = PREV_INSN (get_insn ()->rtl ());
+  rtx_insn *prev_rinsn = PREV_INSN (rinsn);
   gcc_assert (prev_rinsn && vsetvl_insn_p (prev_rinsn));
   return ::get_vl (prev_rinsn);
 }
-- 
2.36.3