Re: [PATCH] RISC-V: Refactor expand_reduction and cleanup enum reduction_type

[Lehua Ding]

Committed, thanks Kito.

On 2023/9/15 16:46, Kito Cheng wrote:

LGTM

On Fri, Sep 15, 2023 at 1:06 PM Lehua Ding > wrote:


This patch refactors expand_reduction, remove the reduction_type
argument
and add insn_flags argument to determine the passing of the operands.
ops has also been modified to restrict it to only two cases and to
remove
operand that are not in use.

gcc/ChangeLog:

         * config/riscv/autovec-opt.md: Adjust.
         * config/riscv/autovec.md: Ditto.
         * config/riscv/riscv-protos.h (enum class): Delete enum
reduction_type.
         (expand_reduction): Adjust expand_reduction prototype.
         * config/riscv/riscv-v.cc (need_mask_operand_p): New helper
function.
         (expand_reduction): Refactor expand_reduction.

---
  gcc/config/riscv/autovec-opt.md | 22 +++-
  gcc/config/riscv/autovec.md     | 51 ++--
  gcc/config/riscv/riscv-protos.h |  9 +
  gcc/config/riscv/riscv-v.cc     | 60 +
  4 files changed, 79 insertions(+), 63 deletions(-)

diff --git a/gcc/config/riscv/autovec-opt.md
b/gcc/config/riscv/autovec-opt.md
index df516849527..b47bae16193 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -1208,7 +1208,8 @@
    "&& 1"
    [(const_int 0)]
  {
-  riscv_vector::expand_reduction (, operands,
+  riscv_vector::expand_reduction (,
riscv_vector::REDUCE_OP,
+                                  operands,
                                    CONST0_RTX
(mode));
    DONE;
  }
@@ -1226,7 +1227,9 @@
    "&& 1"
    [(const_int 0)]
  {
-  riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_UNORDERED,
operands,
+  riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_UNORDERED,
+                                  riscv_vector::REDUCE_OP_FRM_DYN,
+                                  operands,
                                    CONST0_RTX
(mode));
    DONE;
  }
@@ -1245,9 +1248,9 @@
    "&& 1"
    [(const_int 0)]
  {
-  riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_ORDERED, operands,
-                                 operands[1],
-   
  riscv_vector::reduction_type::FOLD_LEFT);

+  riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_ORDERED,
+                                  riscv_vector::REDUCE_OP_FRM_DYN,
+                                  operands, operands[1]);
    DONE;
  }
  [(set_attr "type" "vector")])
@@ -1271,9 +1274,12 @@
    if (rtx_equal_p (operands[4], const0_rtx))
      emit_move_insn (operands[0], operands[1]);
    else
-    riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_ORDERED,
operands,
-                                   operands[1],
- 
  riscv_vector::reduction_type::MASK_LEN_FOLD_LEFT);

+    {
+      rtx ops[] = {operands[0], operands[2], operands[3], operands[4]};
+      riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_ORDERED,
+ 
riscv_vector::REDUCE_OP_M_FRM_DYN,

+                                      ops, operands[1]);
+    }
    DONE;
  }
  [(set_attr "type" "vector")])
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 8537b9d41f6..c6175a3b1f6 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2096,7 +2096,8 @@
    "&& 1"
    [(const_int 0)]
  {
-  riscv_vector::expand_reduction (UNSPEC_REDUC_SUM, operands,
CONST0_RTX (mode));
+  riscv_vector::expand_reduction (UNSPEC_REDUC_SUM,
riscv_vector::REDUCE_OP,
+                                  operands, CONST0_RTX (mode));
    DONE;
  }
  [(set_attr "type" "vector")])
@@ -2108,7 +2109,8 @@
  {
    int prec = GET_MODE_PRECISION (mode);
    rtx min = immed_wide_int_const (wi::min_value (prec, SIGNED),
mode);
-  riscv_vector::expand_reduction (UNSPEC_REDUC_MAX, operands, min);
+  riscv_vector::expand_reduction (UNSPEC_REDUC_MAX,
riscv_vector::REDUCE_OP,
+                                  operands, min);
    DONE;
  })

@@ -2117,7 +2119,8 @@
     (match_operand:VI 1 "register_operand")]
    "TARGET_VECTOR"
  {
-  riscv_vector::expand_reduction (UNSPEC_REDUC_MAXU, operands,
CONST0_RTX (mode));
+  riscv_vector::expand_reduction (UNSPEC_REDUC_MAXU,
riscv_vector::REDUCE_OP,
+                                  operands, CONST0_RTX (mode));
    DONE;
  })

@@ -2128,7 +2131,8 @@
  {
    int prec = GET_MODE_PRECISION (mode);
    rtx max = immed_wide_int_const (wi::max_value (prec, SIGNED),
mode);
-  riscv_vector::expand_reduction 

Re: [PATCH] RISC-V: Refactor expand_reduction and cleanup enum reduction_type

[Kito Cheng via Gcc-patches]

LGTM

On Fri, Sep 15, 2023 at 1:06 PM Lehua Ding  wrote:

> This patch refactors expand_reduction, remove the reduction_type argument
> and add insn_flags argument to determine the passing of the operands.
> ops has also been modified to restrict it to only two cases and to remove
> operand that are not in use.
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md: Adjust.
> * config/riscv/autovec.md: Ditto.
> * config/riscv/riscv-protos.h (enum class): Delete enum
> reduction_type.
> (expand_reduction): Adjust expand_reduction prototype.
> * config/riscv/riscv-v.cc (need_mask_operand_p): New helper
> function.
> (expand_reduction): Refactor expand_reduction.
>
> ---
>  gcc/config/riscv/autovec-opt.md | 22 +++-
>  gcc/config/riscv/autovec.md | 51 ++--
>  gcc/config/riscv/riscv-protos.h |  9 +
>  gcc/config/riscv/riscv-v.cc | 60 +
>  4 files changed, 79 insertions(+), 63 deletions(-)
>
> diff --git a/gcc/config/riscv/autovec-opt.md
> b/gcc/config/riscv/autovec-opt.md
> index df516849527..b47bae16193 100644
> --- a/gcc/config/riscv/autovec-opt.md
> +++ b/gcc/config/riscv/autovec-opt.md
> @@ -1208,7 +1208,8 @@
>"&& 1"
>[(const_int 0)]
>  {
> -  riscv_vector::expand_reduction (, operands,
> +  riscv_vector::expand_reduction (,
> riscv_vector::REDUCE_OP,
> +  operands,
>CONST0_RTX (mode));
>DONE;
>  }
> @@ -1226,7 +1227,9 @@
>"&& 1"
>[(const_int 0)]
>  {
> -  riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_UNORDERED, operands,
> +  riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_UNORDERED,
> +  riscv_vector::REDUCE_OP_FRM_DYN,
> +  operands,
>CONST0_RTX (mode));
>DONE;
>  }
> @@ -1245,9 +1248,9 @@
>"&& 1"
>[(const_int 0)]
>  {
> -  riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_ORDERED, operands,
> - operands[1],
> - riscv_vector::reduction_type::FOLD_LEFT);
> +  riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_ORDERED,
> +  riscv_vector::REDUCE_OP_FRM_DYN,
> +  operands, operands[1]);
>DONE;
>  }
>  [(set_attr "type" "vector")])
> @@ -1271,9 +1274,12 @@
>if (rtx_equal_p (operands[4], const0_rtx))
>  emit_move_insn (operands[0], operands[1]);
>else
> -riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_ORDERED, operands,
> -   operands[1],
> -
>  riscv_vector::reduction_type::MASK_LEN_FOLD_LEFT);
> +{
> +  rtx ops[] = {operands[0], operands[2], operands[3], operands[4]};
> +  riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_ORDERED,
> +  riscv_vector::REDUCE_OP_M_FRM_DYN,
> +  ops, operands[1]);
> +}
>DONE;
>  }
>  [(set_attr "type" "vector")])
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index 8537b9d41f6..c6175a3b1f6 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -2096,7 +2096,8 @@
>"&& 1"
>[(const_int 0)]
>  {
> -  riscv_vector::expand_reduction (UNSPEC_REDUC_SUM, operands, CONST0_RTX
> (mode));
> +  riscv_vector::expand_reduction (UNSPEC_REDUC_SUM,
> riscv_vector::REDUCE_OP,
> +  operands, CONST0_RTX (mode));
>DONE;
>  }
>  [(set_attr "type" "vector")])
> @@ -2108,7 +2109,8 @@
>  {
>int prec = GET_MODE_PRECISION (mode);
>rtx min = immed_wide_int_const (wi::min_value (prec, SIGNED),
> mode);
> -  riscv_vector::expand_reduction (UNSPEC_REDUC_MAX, operands, min);
> +  riscv_vector::expand_reduction (UNSPEC_REDUC_MAX,
> riscv_vector::REDUCE_OP,
> +  operands, min);
>DONE;
>  })
>
> @@ -2117,7 +2119,8 @@
> (match_operand:VI 1 "register_operand")]
>"TARGET_VECTOR"
>  {
> -  riscv_vector::expand_reduction (UNSPEC_REDUC_MAXU, operands, CONST0_RTX
> (mode));
> +  riscv_vector::expand_reduction (UNSPEC_REDUC_MAXU,
> riscv_vector::REDUCE_OP,
> +  operands, CONST0_RTX (mode));
>DONE;
>  })
>
> @@ -2128,7 +2131,8 @@
>  {
>int prec = GET_MODE_PRECISION (mode);
>rtx max = immed_wide_int_const (wi::max_value (prec, SIGNED),
> mode);
> -  riscv_vector::expand_reduction (UNSPEC_REDUC_MIN, operands, max);
> +  riscv_vector::expand_reduction (UNSPEC_REDUC_MIN,
> riscv_vector::REDUCE_OP,
> +  operands, max);
>DONE;
>  })
>
> @@ -2139,7 +2143,8 @@
>  {
>int prec = GET_MODE_PRECISION (mode);
>rtx max = immed_wide_int_const (wi::max_value (prec, UNSIGNED),
> mode);
> -  riscv_vector::expand_reduction (UNSPEC_REDUC_MINU, operands, max);
> +  riscv_vector::expand_reduction (UNSPEC_REDUC_MINU,
> 

[PATCH] RISC-V: Refactor expand_reduction and cleanup enum reduction_type

[Lehua Ding]

This patch refactors expand_reduction, remove the reduction_type argument
and add insn_flags argument to determine the passing of the operands.
ops has also been modified to restrict it to only two cases and to remove
operand that are not in use.

gcc/ChangeLog:

* config/riscv/autovec-opt.md: Adjust.
* config/riscv/autovec.md: Ditto.
* config/riscv/riscv-protos.h (enum class): Delete enum reduction_type.
(expand_reduction): Adjust expand_reduction prototype.
* config/riscv/riscv-v.cc (need_mask_operand_p): New helper function.
(expand_reduction): Refactor expand_reduction.

---
 gcc/config/riscv/autovec-opt.md | 22 +++-
 gcc/config/riscv/autovec.md | 51 ++--
 gcc/config/riscv/riscv-protos.h |  9 +
 gcc/config/riscv/riscv-v.cc | 60 +
 4 files changed, 79 insertions(+), 63 deletions(-)

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index df516849527..b47bae16193 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -1208,7 +1208,8 @@
   "&& 1"
   [(const_int 0)]
 {
-  riscv_vector::expand_reduction (, operands,
+  riscv_vector::expand_reduction (, riscv_vector::REDUCE_OP,
+  operands,
   CONST0_RTX (mode));
   DONE;
 }
@@ -1226,7 +1227,9 @@
   "&& 1"
   [(const_int 0)]
 {
-  riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_UNORDERED, operands,
+  riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_UNORDERED,
+  riscv_vector::REDUCE_OP_FRM_DYN,
+  operands,
   CONST0_RTX (mode));
   DONE;
 }
@@ -1245,9 +1248,9 @@
   "&& 1"
   [(const_int 0)]
 {
-  riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_ORDERED, operands,
- operands[1],
- riscv_vector::reduction_type::FOLD_LEFT);
+  riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_ORDERED,
+  riscv_vector::REDUCE_OP_FRM_DYN,
+  operands, operands[1]);
   DONE;
 }
 [(set_attr "type" "vector")])
@@ -1271,9 +1274,12 @@
   if (rtx_equal_p (operands[4], const0_rtx))
 emit_move_insn (operands[0], operands[1]);
   else
-riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_ORDERED, operands,
-   operands[1],
-   
riscv_vector::reduction_type::MASK_LEN_FOLD_LEFT);
+{
+  rtx ops[] = {operands[0], operands[2], operands[3], operands[4]};
+  riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_ORDERED,
+  riscv_vector::REDUCE_OP_M_FRM_DYN,
+  ops, operands[1]);
+}
   DONE;
 }
 [(set_attr "type" "vector")])
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 8537b9d41f6..c6175a3b1f6 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2096,7 +2096,8 @@
   "&& 1"
   [(const_int 0)]
 {
-  riscv_vector::expand_reduction (UNSPEC_REDUC_SUM, operands, CONST0_RTX 
(mode));
+  riscv_vector::expand_reduction (UNSPEC_REDUC_SUM, riscv_vector::REDUCE_OP,
+  operands, CONST0_RTX (mode));
   DONE;
 }
 [(set_attr "type" "vector")])
@@ -2108,7 +2109,8 @@
 {
   int prec = GET_MODE_PRECISION (mode);
   rtx min = immed_wide_int_const (wi::min_value (prec, SIGNED), mode);
-  riscv_vector::expand_reduction (UNSPEC_REDUC_MAX, operands, min);
+  riscv_vector::expand_reduction (UNSPEC_REDUC_MAX, riscv_vector::REDUCE_OP,
+  operands, min);
   DONE;
 })

@@ -2117,7 +2119,8 @@
(match_operand:VI 1 "register_operand")]
   "TARGET_VECTOR"
 {
-  riscv_vector::expand_reduction (UNSPEC_REDUC_MAXU, operands, CONST0_RTX 
(mode));
+  riscv_vector::expand_reduction (UNSPEC_REDUC_MAXU, riscv_vector::REDUCE_OP,
+  operands, CONST0_RTX (mode));
   DONE;
 })

@@ -2128,7 +2131,8 @@
 {
   int prec = GET_MODE_PRECISION (mode);
   rtx max = immed_wide_int_const (wi::max_value (prec, SIGNED), mode);
-  riscv_vector::expand_reduction (UNSPEC_REDUC_MIN, operands, max);
+  riscv_vector::expand_reduction (UNSPEC_REDUC_MIN, riscv_vector::REDUCE_OP,
+  operands, max);
   DONE;
 })

@@ -2139,7 +2143,8 @@
 {
   int prec = GET_MODE_PRECISION (mode);
   rtx max = immed_wide_int_const (wi::max_value (prec, UNSIGNED), mode);
-  riscv_vector::expand_reduction (UNSPEC_REDUC_MINU, operands, max);
+  riscv_vector::expand_reduction (UNSPEC_REDUC_MINU, riscv_vector::REDUCE_OP,
+  operands, max);
   DONE;
 })

@@ -2148,7 +2153,8 @@
(match_operand:VI 1 "register_operand")]
   "TARGET_VECTOR"
 {
-  riscv_vector::expand_reduction (UNSPEC_REDUC_AND, operands, CONSTM1_RTX 
(mode));
+