Re: [PATCH] RISC-V: Support (set (mem) (const_poly_int))

2022-10-23 Thread Kito Cheng via Gcc-patches 
Merged two changes into one patch, and committed to master :)

On Mon, Oct 24, 2022 at 10:28 AM  wrote:
>
> From: Ju-Zhe Zhong 
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_legitimize_move): Adjust using 
> force_reg.
>
> ---
>  gcc/config/riscv/riscv.cc | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 98374a922d1..1fd34f6ae8d 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -1967,9 +1967,7 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx 
> src)
>*/
>if (MEM_P (dest))
> {
> - rtx tmp = gen_reg_rtx (mode);
> - emit_move_insn (tmp, src);
> - emit_move_insn (dest, tmp);
> + emit_move_insn (dest, force_reg (mode, src));
>   return true;
> }
>poly_int64 value = rtx_to_poly_int64 (src);
> --
> 2.36.1
>

[PATCH] RISC-V: Support (set (mem) (const_poly_int))

2022-10-23 Thread juzhe . zhong 
From: Ju-Zhe Zhong 

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_legitimize_move): Adjust using force_reg.

---
 gcc/config/riscv/riscv.cc | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 98374a922d1..1fd34f6ae8d 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1967,9 +1967,7 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx 
src)
   */
   if (MEM_P (dest))
{
- rtx tmp = gen_reg_rtx (mode);
- emit_move_insn (tmp, src);
- emit_move_insn (dest, tmp);
+ emit_move_insn (dest, force_reg (mode, src));
  return true;
}
   poly_int64 value = rtx_to_poly_int64 (src);
-- 
2.36.1

Re: Re: [PATCH] RISC-V: Support (set (mem) (const_poly_int))

2022-10-23 Thread juzhe.zh...@rivai.ai 
Address comments. Fix it soon.



juzhe.zh...@rivai.ai
 
From: Andrew Pinski
Date: 2022-10-24 10:14
To: juzhe.zhong
CC: gcc-patches; kito.cheng
Subject: Re: [PATCH] RISC-V: Support (set (mem) (const_poly_int))
On Sun, Oct 23, 2022 at 7:04 PM  wrote:
>
> From: Ju-Zhe Zhong 
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_legitimize_move): Support (set (mem) 
> (const_poly_int)).
>
> ---
>  gcc/config/riscv/riscv.cc | 14 ++
>  1 file changed, 14 insertions(+)
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 90a39047dd7..f7694ba043c 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -1958,6 +1958,20 @@ riscv_legitimize_move (machine_mode mode, rtx dest, 
> rtx src)
>  {
>if (CONST_POLY_INT_P (src))
>  {
> +  /*
> +   Handle:
> + (insn 183 182 184 6 (set (mem:QI (plus:DI (reg/f:DI 156)
> + (const_int 96 [0x60])) [0  S1 A8])
> + (const_poly_int:QI [8, 8]))
> +   "../../../../riscv-gcc/libgcc/unwind-dw2.c":1579:3 -1 (nil))
> +  */
> +  if (MEM_P (dest))
> +   {
> + rtx tmp = gen_reg_rtx (mode);
> + emit_move_insn (tmp, src);
> + emit_move_insn (dest, tmp);
 
Couldn't you just use force_reg here instead of the above?
Something like:
emit_move_insn (dest, force_reg (mode, src));
 
Thanks,
Andrew Pinski
 
> + return true;
> +   }
>poly_int64 value = rtx_to_poly_int64 (src);
>if (!value.is_constant () && !TARGET_VECTOR)
> {
> --
> 2.36.1
>

Re: [PATCH] RISC-V: Support (set (mem) (const_poly_int))

2022-10-23 Thread Andrew Pinski via Gcc-patches 
On Sun, Oct 23, 2022 at 7:04 PM  wrote:
>
> From: Ju-Zhe Zhong 
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_legitimize_move): Support (set (mem) 
> (const_poly_int)).
>
> ---
>  gcc/config/riscv/riscv.cc | 14 ++
>  1 file changed, 14 insertions(+)
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 90a39047dd7..f7694ba043c 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -1958,6 +1958,20 @@ riscv_legitimize_move (machine_mode mode, rtx dest, 
> rtx src)
>  {
>if (CONST_POLY_INT_P (src))
>  {
> +  /*
> +   Handle:
> + (insn 183 182 184 6 (set (mem:QI (plus:DI (reg/f:DI 156)
> + (const_int 96 [0x60])) [0  S1 A8])
> + (const_poly_int:QI [8, 8]))
> +   "../../../../riscv-gcc/libgcc/unwind-dw2.c":1579:3 -1 (nil))
> +  */
> +  if (MEM_P (dest))
> +   {
> + rtx tmp = gen_reg_rtx (mode);
> + emit_move_insn (tmp, src);
> + emit_move_insn (dest, tmp);

Couldn't you just use force_reg here instead of the above?
Something like:
emit_move_insn (dest, force_reg (mode, src));

Thanks,
Andrew Pinski

> + return true;
> +   }
>poly_int64 value = rtx_to_poly_int64 (src);
>if (!value.is_constant () && !TARGET_VECTOR)
> {
> --
> 2.36.1
>

[PATCH] RISC-V: Support (set (mem) (const_poly_int))

2022-10-23 Thread juzhe . zhong 
From: Ju-Zhe Zhong 

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_legitimize_move): Support (set (mem) 
(const_poly_int)).

---
 gcc/config/riscv/riscv.cc | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 90a39047dd7..f7694ba043c 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1958,6 +1958,20 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx 
src)
 {
   if (CONST_POLY_INT_P (src))
 {
+  /*
+   Handle:
+ (insn 183 182 184 6 (set (mem:QI (plus:DI (reg/f:DI 156)
+ (const_int 96 [0x60])) [0  S1 A8])
+ (const_poly_int:QI [8, 8]))
+   "../../../../riscv-gcc/libgcc/unwind-dw2.c":1579:3 -1 (nil))
+  */
+  if (MEM_P (dest))
+   {
+ rtx tmp = gen_reg_rtx (mode);
+ emit_move_insn (tmp, src);
+ emit_move_insn (dest, tmp);
+ return true;
+   }
   poly_int64 value = rtx_to_poly_int64 (src);
   if (!value.is_constant () && !TARGET_VECTOR)
{
-- 
2.36.1

Re: [PATCH] RISC-V: Support (set (mem) (const_poly_int)) handling and remove TI/TF.

2022-10-23 Thread juzhe.zh...@rivai.ai 
I made a mistake in this patch. I mixed 2 commits into a single patch.
Sorry about that. Please ignore this patch. Thanks.



juzhe.zh...@rivai.ai
 
From: juzhe.zhong
Date: 2022-10-24 09:53
To: gcc-patches
CC: kito.cheng; palmer; Ju-Zhe Zhong
Subject: [PATCH] RISC-V: Support (set (mem) (const_poly_int)) handling and 
remove TI/TF.
From: Ju-Zhe Zhong 
 
gcc/ChangeLog:
 
* config/riscv/riscv-vector-switch.def (ENTRY): Remove TI/TF.
* config/riscv/riscv.cc (riscv_legitimize_move): Support (set (mem) 
(const_poly_int)).
 
---
gcc/config/riscv/riscv-vector-switch.def |  4 
gcc/config/riscv/riscv.cc| 14 ++
2 files changed, 14 insertions(+), 4 deletions(-)
 
diff --git a/gcc/config/riscv/riscv-vector-switch.def 
b/gcc/config/riscv/riscv-vector-switch.def
index cacfccb6d29..ee8ebd5f1cc 100644
--- a/gcc/config/riscv/riscv-vector-switch.def
+++ b/gcc/config/riscv/riscv-vector-switch.def
@@ -155,10 +155,6 @@ ENTRY (VNx4DF, TARGET_VECTOR_FP64)
ENTRY (VNx2DF, TARGET_VECTOR_FP64)
ENTRY (VNx1DF, TARGET_VECTOR_FP64)
-/* SEW = 128. Disable all of them.  */
-ENTRY (VNx2TI, false)
-ENTRY (VNx2TF, false)
-
#undef TARGET_VECTOR_FP32
#undef TARGET_VECTOR_FP64
#undef ENTRY
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 90a39047dd7..f7694ba043c 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1958,6 +1958,20 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx 
src)
{
   if (CONST_POLY_INT_P (src))
 {
+  /*
+ Handle:
+   (insn 183 182 184 6 (set (mem:QI (plus:DI (reg/f:DI 156)
+   (const_int 96 [0x60])) [0  S1 A8])
+   (const_poly_int:QI [8, 8]))
+ "../../../../riscv-gcc/libgcc/unwind-dw2.c":1579:3 -1 (nil))
+  */
+  if (MEM_P (dest))
+ {
+   rtx tmp = gen_reg_rtx (mode);
+   emit_move_insn (tmp, src);
+   emit_move_insn (dest, tmp);
+   return true;
+ }
   poly_int64 value = rtx_to_poly_int64 (src);
   if (!value.is_constant () && !TARGET_VECTOR)
{
-- 
2.36.1

[PATCH] RISC-V: Support (set (mem) (const_poly_int)) handling and remove TI/TF.

2022-10-23 Thread juzhe . zhong 
From: Ju-Zhe Zhong 

gcc/ChangeLog:

* config/riscv/riscv-vector-switch.def (ENTRY): Remove TI/TF.
* config/riscv/riscv.cc (riscv_legitimize_move): Support (set (mem) 
(const_poly_int)).

---
 gcc/config/riscv/riscv-vector-switch.def |  4 
 gcc/config/riscv/riscv.cc| 14 ++
 2 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/gcc/config/riscv/riscv-vector-switch.def 
b/gcc/config/riscv/riscv-vector-switch.def
index cacfccb6d29..ee8ebd5f1cc 100644
--- a/gcc/config/riscv/riscv-vector-switch.def
+++ b/gcc/config/riscv/riscv-vector-switch.def
@@ -155,10 +155,6 @@ ENTRY (VNx4DF, TARGET_VECTOR_FP64)
 ENTRY (VNx2DF, TARGET_VECTOR_FP64)
 ENTRY (VNx1DF, TARGET_VECTOR_FP64)
 
-/* SEW = 128. Disable all of them.  */
-ENTRY (VNx2TI, false)
-ENTRY (VNx2TF, false)
-
 #undef TARGET_VECTOR_FP32
 #undef TARGET_VECTOR_FP64
 #undef ENTRY
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 90a39047dd7..f7694ba043c 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1958,6 +1958,20 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx 
src)
 {
   if (CONST_POLY_INT_P (src))
 {
+  /*
+   Handle:
+ (insn 183 182 184 6 (set (mem:QI (plus:DI (reg/f:DI 156)
+ (const_int 96 [0x60])) [0  S1 A8])
+ (const_poly_int:QI [8, 8]))
+   "../../../../riscv-gcc/libgcc/unwind-dw2.c":1579:3 -1 (nil))
+  */
+  if (MEM_P (dest))
+   {
+ rtx tmp = gen_reg_rtx (mode);
+ emit_move_insn (tmp, src);
+ emit_move_insn (dest, tmp);
+ return true;
+   }
   poly_int64 value = rtx_to_poly_int64 (src);
   if (!value.is_constant () && !TARGET_VECTOR)
{
-- 
2.36.1