RE: [PATCH] RISC-V: Support VLS modes reduction[PR111153]

2023-09-18 Thread Li, Pan2 via Gcc-patches 
Committed, thanks Kito.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Kito Cheng via Gcc-patches
Sent: Monday, September 18, 2023 4:20 PM
To: Juzhe-Zhong 
Cc: gcc-patches@gcc.gnu.org; kito.ch...@sifive.com; jeffreya...@gmail.com; 
rdapp@gmail.com
Subject: Re: [PATCH] RISC-V: Support VLS modes reduction[PR53]

LGTM

On Sun, Sep 17, 2023 at 10:07 AM Juzhe-Zhong  wrote:
>
> This patch supports VLS reduction vectorization.
>
> It can optimize the current reduction vectorization codegen with current COST 
> model.
>
> #define DEF_REDUC_PLUS(TYPE)\
> TYPE __attribute__ ((noinline, noclone))\
> reduc_plus_##TYPE (TYPE * __restrict a, int n)  \
> {   \
>   TYPE r = 0;   \
>   for (int i = 0; i < n; ++i)   \
> r += a[i];  \
>   return r; \
> }
>
> #define TEST_PLUS(T)\
>   T (int32_t)   \
>
> TEST_PLUS (DEF_REDUC_PLUS)
>
>
> Before this patch:
>
> vle32.v v2,0(a5)
> addia5,a5,16
> vadd.vv v1,v1,v2
> bne a5,a4,.L4
> lui a4,%hi(.LC0)
> lui a5,%hi(.LC1)
> addia4,a4,%lo(.LC0)
> vlm.v   v0,0(a4)
> addia5,a5,%lo(.LC1)
> andia1,a1,-4
> vmv1r.v v2,v3
> vlm.v   v4,0(a5)
> vcompress.vmv2,v1,v0
> vmv1r.v v0,v4
> vadd.vv v1,v2,v1
> vcompress.vmv3,v1,v0
> vadd.vv v3,v3,v1
> vmv.x.s a0,v3
> sext.w  a0,a0
> beq a3,a1,.L12
>
> After this patch:
>
> vle32.v v2,0(a5)
> addia5,a5,16
> vadd.vv v1,v1,v2
> bne a5,a4,.L4
> li  a5,0
> andia1,a1,-4
> vmv.s.x v2,a5
> vredsum.vs  v1,v1,v2
> vmv.x.s a0,v1
> beq a3,a1,.L12
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md: Add VLS modes.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/vls/def.h: Add VLS mode reduction case.
> * gcc.target/riscv/rvv/autovec/vls/reduc-1.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-10.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-11.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-12.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-13.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-14.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-15.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-16.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-17.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-18.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-19.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-2.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-20.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-21.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-3.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-4.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-5.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-6.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-7.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-8.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-9.c: New test.
>
> ---
>  gcc/config/riscv/autovec.md   |  2 +-
>  .../gcc.target/riscv/rvv/autovec/vls/def.h| 30 +++
>  .../riscv/rvv/autovec/vls/reduc-1.c   | 31 +++
>  .../riscv/rvv/autovec/vls/reduc-10.c  | 50 
>  .../riscv/rvv/autovec/vls/reduc-11.c  | 46 +++
>  .../riscv/rvv/autovec/vls/reduc-12.c  | 30 +++
>  .../riscv/rvv/autovec/vls/reduc-13.c  | 28 +++
>  .../riscv/rvv/autovec/vls/reduc-14.c  | 26 ++
>  .../riscv/rvv/autovec/vls/reduc-15.c  | 81 +++
>  .../riscv/rvv/autovec/vls/reduc-16.c  | 75 +
>  .../riscv/rvv/autovec/vls/reduc-17.c  | 69 
>  .../riscv/rvv/autovec/vls/reduc-18.c  | 63 +++
>  .../riscv/rvv/autovec/vls/reduc-19.c  | 18 +
>  .../riscv/rvv/autovec/vls/reduc-2.c   | 29 +++
>  .../riscv/rvv/autovec/vls/reduc-20.c  | 17 
>  .../riscv/rvv/autovec/vls/reduc-21.c  | 16 
>  .../riscv/rvv/autovec/vls/reduc-3

Re: [PATCH] RISC-V: Support VLS modes reduction[PR111153]

2023-09-18 Thread Kito Cheng via Gcc-patches 
LGTM

On Sun, Sep 17, 2023 at 10:07 AM Juzhe-Zhong  wrote:
>
> This patch supports VLS reduction vectorization.
>
> It can optimize the current reduction vectorization codegen with current COST 
> model.
>
> #define DEF_REDUC_PLUS(TYPE)\
> TYPE __attribute__ ((noinline, noclone))\
> reduc_plus_##TYPE (TYPE * __restrict a, int n)  \
> {   \
>   TYPE r = 0;   \
>   for (int i = 0; i < n; ++i)   \
> r += a[i];  \
>   return r; \
> }
>
> #define TEST_PLUS(T)\
>   T (int32_t)   \
>
> TEST_PLUS (DEF_REDUC_PLUS)
>
>
> Before this patch:
>
> vle32.v v2,0(a5)
> addia5,a5,16
> vadd.vv v1,v1,v2
> bne a5,a4,.L4
> lui a4,%hi(.LC0)
> lui a5,%hi(.LC1)
> addia4,a4,%lo(.LC0)
> vlm.v   v0,0(a4)
> addia5,a5,%lo(.LC1)
> andia1,a1,-4
> vmv1r.v v2,v3
> vlm.v   v4,0(a5)
> vcompress.vmv2,v1,v0
> vmv1r.v v0,v4
> vadd.vv v1,v2,v1
> vcompress.vmv3,v1,v0
> vadd.vv v3,v3,v1
> vmv.x.s a0,v3
> sext.w  a0,a0
> beq a3,a1,.L12
>
> After this patch:
>
> vle32.v v2,0(a5)
> addia5,a5,16
> vadd.vv v1,v1,v2
> bne a5,a4,.L4
> li  a5,0
> andia1,a1,-4
> vmv.s.x v2,a5
> vredsum.vs  v1,v1,v2
> vmv.x.s a0,v1
> beq a3,a1,.L12
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md: Add VLS modes.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/vls/def.h: Add VLS mode reduction case.
> * gcc.target/riscv/rvv/autovec/vls/reduc-1.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-10.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-11.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-12.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-13.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-14.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-15.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-16.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-17.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-18.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-19.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-2.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-20.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-21.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-3.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-4.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-5.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-6.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-7.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-8.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-9.c: New test.
>
> ---
>  gcc/config/riscv/autovec.md   |  2 +-
>  .../gcc.target/riscv/rvv/autovec/vls/def.h| 30 +++
>  .../riscv/rvv/autovec/vls/reduc-1.c   | 31 +++
>  .../riscv/rvv/autovec/vls/reduc-10.c  | 50 
>  .../riscv/rvv/autovec/vls/reduc-11.c  | 46 +++
>  .../riscv/rvv/autovec/vls/reduc-12.c  | 30 +++
>  .../riscv/rvv/autovec/vls/reduc-13.c  | 28 +++
>  .../riscv/rvv/autovec/vls/reduc-14.c  | 26 ++
>  .../riscv/rvv/autovec/vls/reduc-15.c  | 81 +++
>  .../riscv/rvv/autovec/vls/reduc-16.c  | 75 +
>  .../riscv/rvv/autovec/vls/reduc-17.c  | 69 
>  .../riscv/rvv/autovec/vls/reduc-18.c  | 63 +++
>  .../riscv/rvv/autovec/vls/reduc-19.c  | 18 +
>  .../riscv/rvv/autovec/vls/reduc-2.c   | 29 +++
>  .../riscv/rvv/autovec/vls/reduc-20.c  | 17 
>  .../riscv/rvv/autovec/vls/reduc-21.c  | 16 
>  .../riscv/rvv/autovec/vls/reduc-3.c   | 27 +++
>  .../riscv/rvv/autovec/vls/reduc-4.c   | 25 ++
>  .../riscv/rvv/autovec/vls/reduc-5.c   | 18 +
>  .../riscv/rvv/autovec/vls/reduc-6.c   | 17 
>  .../riscv/rvv/autovec/vls/reduc-7.c   | 16 
>  .../riscv/rvv/autovec/vls/reduc-8.c   | 58 +
>  .../riscv/rvv/autovec/vls/reduc-9.c   | 54 +
>  23 files changed, 825 insertions(+), 1 deletion(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-10.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/r

[PATCH] RISC-V: Support VLS modes reduction[PR111153]

2023-09-16 Thread Juzhe-Zhong 
This patch supports VLS reduction vectorization.

It can optimize the current reduction vectorization codegen with current COST 
model.

#define DEF_REDUC_PLUS(TYPE)\
TYPE __attribute__ ((noinline, noclone))\
reduc_plus_##TYPE (TYPE * __restrict a, int n)  \
{   \
  TYPE r = 0;   \
  for (int i = 0; i < n; ++i)   \
r += a[i];  \
  return r; \
}

#define TEST_PLUS(T)\
  T (int32_t)   \

TEST_PLUS (DEF_REDUC_PLUS)


Before this patch:

vle32.v v2,0(a5)
addia5,a5,16
vadd.vv v1,v1,v2
bne a5,a4,.L4
lui a4,%hi(.LC0)
lui a5,%hi(.LC1)
addia4,a4,%lo(.LC0)
vlm.v   v0,0(a4)
addia5,a5,%lo(.LC1)
andia1,a1,-4
vmv1r.v v2,v3
vlm.v   v4,0(a5)
vcompress.vmv2,v1,v0
vmv1r.v v0,v4
vadd.vv v1,v2,v1
vcompress.vmv3,v1,v0
vadd.vv v3,v3,v1
vmv.x.s a0,v3
sext.w  a0,a0
beq a3,a1,.L12

After this patch:

vle32.v v2,0(a5)
addia5,a5,16
vadd.vv v1,v1,v2
bne a5,a4,.L4
li  a5,0
andia1,a1,-4
vmv.s.x v2,a5
vredsum.vs  v1,v1,v2
vmv.x.s a0,v1
beq a3,a1,.L12

gcc/ChangeLog:

* config/riscv/autovec.md: Add VLS modes.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vls/def.h: Add VLS mode reduction case.
* gcc.target/riscv/rvv/autovec/vls/reduc-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-10.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-11.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-12.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-13.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-14.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-15.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-16.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-17.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-18.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-19.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-20.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-21.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-5.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-6.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-7.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-8.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-9.c: New test.

---
 gcc/config/riscv/autovec.md   |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/def.h| 30 +++
 .../riscv/rvv/autovec/vls/reduc-1.c   | 31 +++
 .../riscv/rvv/autovec/vls/reduc-10.c  | 50 
 .../riscv/rvv/autovec/vls/reduc-11.c  | 46 +++
 .../riscv/rvv/autovec/vls/reduc-12.c  | 30 +++
 .../riscv/rvv/autovec/vls/reduc-13.c  | 28 +++
 .../riscv/rvv/autovec/vls/reduc-14.c  | 26 ++
 .../riscv/rvv/autovec/vls/reduc-15.c  | 81 +++
 .../riscv/rvv/autovec/vls/reduc-16.c  | 75 +
 .../riscv/rvv/autovec/vls/reduc-17.c  | 69 
 .../riscv/rvv/autovec/vls/reduc-18.c  | 63 +++
 .../riscv/rvv/autovec/vls/reduc-19.c  | 18 +
 .../riscv/rvv/autovec/vls/reduc-2.c   | 29 +++
 .../riscv/rvv/autovec/vls/reduc-20.c  | 17 
 .../riscv/rvv/autovec/vls/reduc-21.c  | 16 
 .../riscv/rvv/autovec/vls/reduc-3.c   | 27 +++
 .../riscv/rvv/autovec/vls/reduc-4.c   | 25 ++
 .../riscv/rvv/autovec/vls/reduc-5.c   | 18 +
 .../riscv/rvv/autovec/vls/reduc-6.c   | 17 
 .../riscv/rvv/autovec/vls/reduc-7.c   | 16 
 .../riscv/rvv/autovec/vls/reduc-8.c   | 58 +
 .../riscv/rvv/autovec/vls/reduc-9.c   | 54 +
 23 files changed, 825 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-11.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-12.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-13.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-14.c
 create mode 100644 gcc/testsui