Re: [PATCH] RISC-V: Support cond vmulh.vv and vmulu.vv

2023-09-13 Thread Lehua Ding 

Committed, thanks Kito.

On 2023/9/13 16:50, Kito Cheng wrote:

LGTM, thanks :)

On Wed, Sep 13, 2023 at 12:25 AM Lehua Ding  wrote:


This patch adds combine patterns to combine vmulh[u].vv + vcond_mask
to mask vmulh[u].vv. For vmulsu.vv, it can not be produced in midend
currently. We will send another patch to take this issue.

gcc/ChangeLog:

 * config/riscv/autovec-opt.md (*cond_3_highpart):
 New combine pattern.
 * config/riscv/autovec.md (smul3_highpart): Mrege smul and umul.
 (3_highpart): Merged pattern.
 (umul3_highpart): Mrege smul and umul.
 * config/riscv/vector-iterators.md (umul): New iterators.
 (UNSPEC_VMULHU): New iterators.

gcc/testsuite/ChangeLog:

 * gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c: New test.
 * gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c: New test.
 * gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c: New test.
 * gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c: New test.

---
  gcc/config/riscv/autovec-opt.md   | 23 -
  gcc/config/riscv/autovec.md   | 22 ++--
  gcc/config/riscv/vector-iterators.md  |  4 +++
  .../riscv/rvv/autovec/cond/cond_mulh-1.c  | 29 
  .../riscv/rvv/autovec/cond/cond_mulh-2.c  | 30 
  .../riscv/rvv/autovec/cond/cond_mulh_run-1.c  | 32 +
  .../riscv/rvv/autovec/cond/cond_mulh_run-2.c  | 34 +++
  7 files changed, 154 insertions(+), 20 deletions(-)
  create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c
  create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c
  create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c
  create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 0d2721f0b29..552be48bf73 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -970,6 +970,28 @@
  }
   [(set_attr "type" "vnshift")])

+;; Combine vmulh.vv/vmulhu.vv + vcond_mask
+(define_insn_and_split "*cond_3_highpart"
+   [(set (match_operand:VFULLI 0 "register_operand")
+(if_then_else:VFULLI
+  (match_operand: 1 "register_operand")
+  (mulh:VFULLI
+(match_operand:VFULLI 2 "register_operand")
+(match_operand:VFULLI 3 "register_operand"))
+  (match_operand:VFULLI 4 "register_operand")))]
+   "TARGET_VECTOR && can_create_pseudo_p ()"
+   "#"
+   "&& 1"
+   [(const_int 0)]
+{
+  insn_code icode = code_for_pred_mulh (, mode);
+  rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[4],
+   gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
+  riscv_vector::expand_cond_len_binop (icode, ops);
+   DONE;
+}
+[(set_attr "type" "vector")])
+
  ;; 
=
  ;; Combine extend + binop to widen_binop
  ;; 
=
@@ -1172,7 +1194,6 @@
  }
  [(set_attr "type" "vfwmul")])

-
  ;; 
=
  ;; Misc combine patterns
  ;; 
=
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index e9dd40af935..b4ac22bb97b 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1569,9 +1569,9 @@
  ;; - vmulhu.vv
  ;; -

-(define_insn_and_split "smul3_highpart"
+(define_insn_and_split "3_highpart"
[(set (match_operand:VFULLI 0 "register_operand")
-(smul_highpart:VFULLI
+(mulh:VFULLI
(match_operand:VFULLI 1 "register_operand")
(match_operand:VFULLI 2 "register_operand")))]
"TARGET_VECTOR && can_create_pseudo_p ()"
@@ -1579,23 +1579,7 @@
"&& 1"
[(const_int 0)]
  {
-  insn_code icode = code_for_pred_mulh (UNSPEC_VMULHS, mode);
-  riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
-  DONE;
-}
-[(set_attr "type" "vimul")])
-
-(define_insn_and_split "umul3_highpart"
-  [(set (match_operand:VFULLI 0 "register_operand")
-(umul_highpart:VFULLI
-  (match_operand:VFULLI 1 "register_operand")
-  (match_operand:VFULLI 2 "register_operand")))]
-  "TARGET_VECTOR && can_create_pseudo_p ()"
-  "#"
-  "&& 1"
-  [(const_int 0)]
-{
-  insn_code icode = code_for_pred_mulh (UNSPEC_VMULHU, mode);
+  insn_code icode = code_for_pred_mulh (, mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
DONE;
  }
diff --git a/gcc/config/riscv/vector-iterators.md 
b/gcc/config/riscv/vector-iterators.md
index 2f7f7cbe08c..e70a9bc5c74 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/

Re: [PATCH] RISC-V: Support cond vmulh.vv and vmulu.vv

2023-09-13 Thread Kito Cheng via Gcc-patches 
LGTM, thanks :)

On Wed, Sep 13, 2023 at 12:25 AM Lehua Ding  wrote:
>
> This patch adds combine patterns to combine vmulh[u].vv + vcond_mask
> to mask vmulh[u].vv. For vmulsu.vv, it can not be produced in midend
> currently. We will send another patch to take this issue.
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md (*cond_3_highpart):
> New combine pattern.
> * config/riscv/autovec.md (smul3_highpart): Mrege smul and umul.
> (3_highpart): Merged pattern.
> (umul3_highpart): Mrege smul and umul.
> * config/riscv/vector-iterators.md (umul): New iterators.
> (UNSPEC_VMULHU): New iterators.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c: New test.
> * gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c: New test.
> * gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c: New test.
> * gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c: New test.
>
> ---
>  gcc/config/riscv/autovec-opt.md   | 23 -
>  gcc/config/riscv/autovec.md   | 22 ++--
>  gcc/config/riscv/vector-iterators.md  |  4 +++
>  .../riscv/rvv/autovec/cond/cond_mulh-1.c  | 29 
>  .../riscv/rvv/autovec/cond/cond_mulh-2.c  | 30 
>  .../riscv/rvv/autovec/cond/cond_mulh_run-1.c  | 32 +
>  .../riscv/rvv/autovec/cond/cond_mulh_run-2.c  | 34 +++
>  7 files changed, 154 insertions(+), 20 deletions(-)
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c
>
> diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
> index 0d2721f0b29..552be48bf73 100644
> --- a/gcc/config/riscv/autovec-opt.md
> +++ b/gcc/config/riscv/autovec-opt.md
> @@ -970,6 +970,28 @@
>  }
>   [(set_attr "type" "vnshift")])
>
> +;; Combine vmulh.vv/vmulhu.vv + vcond_mask
> +(define_insn_and_split "*cond_3_highpart"
> +   [(set (match_operand:VFULLI 0 "register_operand")
> +(if_then_else:VFULLI
> +  (match_operand: 1 "register_operand")
> +  (mulh:VFULLI
> +(match_operand:VFULLI 2 "register_operand")
> +(match_operand:VFULLI 3 "register_operand"))
> +  (match_operand:VFULLI 4 "register_operand")))]
> +   "TARGET_VECTOR && can_create_pseudo_p ()"
> +   "#"
> +   "&& 1"
> +   [(const_int 0)]
> +{
> +  insn_code icode = code_for_pred_mulh (, mode);
> +  rtx ops[] = {operands[0], operands[1], operands[2], operands[3], 
> operands[4],
> +   gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
> +  riscv_vector::expand_cond_len_binop (icode, ops);
> +   DONE;
> +}
> +[(set_attr "type" "vector")])
> +
>  ;; 
> =
>  ;; Combine extend + binop to widen_binop
>  ;; 
> =
> @@ -1172,7 +1194,6 @@
>  }
>  [(set_attr "type" "vfwmul")])
>
> -
>  ;; 
> =
>  ;; Misc combine patterns
>  ;; 
> =
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index e9dd40af935..b4ac22bb97b 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -1569,9 +1569,9 @@
>  ;; - vmulhu.vv
>  ;; -
>
> -(define_insn_and_split "smul3_highpart"
> +(define_insn_and_split "3_highpart"
>[(set (match_operand:VFULLI 0 "register_operand")
> -(smul_highpart:VFULLI
> +(mulh:VFULLI
>(match_operand:VFULLI 1 "register_operand")
>(match_operand:VFULLI 2 "register_operand")))]
>"TARGET_VECTOR && can_create_pseudo_p ()"
> @@ -1579,23 +1579,7 @@
>"&& 1"
>[(const_int 0)]
>  {
> -  insn_code icode = code_for_pred_mulh (UNSPEC_VMULHS, mode);
> -  riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
> -  DONE;
> -}
> -[(set_attr "type" "vimul")])
> -
> -(define_insn_and_split "umul3_highpart"
> -  [(set (match_operand:VFULLI 0 "register_operand")
> -(umul_highpart:VFULLI
> -  (match_operand:VFULLI 1 "register_operand")
> -  (match_operand:VFULLI 2 "register_operand")))]
> -  "TARGET_VECTOR && can_create_pseudo_p ()"
> -  "#"
> -  "&& 1"
> -  [(const_int 0)]
> -{
> -  insn_code icode = code_for_pred_mulh (UNSPEC_VMULHU, mode);
> +  insn_code icode = code_for_pred_mulh (, mode);
>riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
>DONE;
>  }
> diff --git a/gcc/config/riscv/vector-iterators.md 
> b/gcc

[PATCH] RISC-V: Support cond vmulh.vv and vmulu.vv

2023-09-12 Thread Lehua Ding 
This patch adds combine patterns to combine vmulh[u].vv + vcond_mask
to mask vmulh[u].vv. For vmulsu.vv, it can not be produced in midend
currently. We will send another patch to take this issue.

gcc/ChangeLog:

* config/riscv/autovec-opt.md (*cond_3_highpart):
New combine pattern.
* config/riscv/autovec.md (smul3_highpart): Mrege smul and umul.
(3_highpart): Merged pattern.
(umul3_highpart): Mrege smul and umul.
* config/riscv/vector-iterators.md (umul): New iterators.
(UNSPEC_VMULHU): New iterators.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c: New test.

---
 gcc/config/riscv/autovec-opt.md   | 23 -
 gcc/config/riscv/autovec.md   | 22 ++--
 gcc/config/riscv/vector-iterators.md  |  4 +++
 .../riscv/rvv/autovec/cond/cond_mulh-1.c  | 29 
 .../riscv/rvv/autovec/cond/cond_mulh-2.c  | 30 
 .../riscv/rvv/autovec/cond/cond_mulh_run-1.c  | 32 +
 .../riscv/rvv/autovec/cond/cond_mulh_run-2.c  | 34 +++
 7 files changed, 154 insertions(+), 20 deletions(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 0d2721f0b29..552be48bf73 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -970,6 +970,28 @@
 }
  [(set_attr "type" "vnshift")])
 
+;; Combine vmulh.vv/vmulhu.vv + vcond_mask
+(define_insn_and_split "*cond_3_highpart"
+   [(set (match_operand:VFULLI 0 "register_operand")
+(if_then_else:VFULLI
+  (match_operand: 1 "register_operand")
+  (mulh:VFULLI
+(match_operand:VFULLI 2 "register_operand")
+(match_operand:VFULLI 3 "register_operand"))
+  (match_operand:VFULLI 4 "register_operand")))]
+   "TARGET_VECTOR && can_create_pseudo_p ()"
+   "#"
+   "&& 1"
+   [(const_int 0)]
+{
+  insn_code icode = code_for_pred_mulh (, mode);
+  rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[4],
+   gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
+  riscv_vector::expand_cond_len_binop (icode, ops);
+   DONE;
+}
+[(set_attr "type" "vector")])
+
 ;; 
=
 ;; Combine extend + binop to widen_binop
 ;; 
=
@@ -1172,7 +1194,6 @@
 }
 [(set_attr "type" "vfwmul")])
 
-
 ;; 
=
 ;; Misc combine patterns
 ;; 
=
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index e9dd40af935..b4ac22bb97b 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1569,9 +1569,9 @@
 ;; - vmulhu.vv
 ;; -
 
-(define_insn_and_split "smul3_highpart"
+(define_insn_and_split "3_highpart"
   [(set (match_operand:VFULLI 0 "register_operand")
-(smul_highpart:VFULLI
+(mulh:VFULLI
   (match_operand:VFULLI 1 "register_operand")
   (match_operand:VFULLI 2 "register_operand")))]
   "TARGET_VECTOR && can_create_pseudo_p ()"
@@ -1579,23 +1579,7 @@
   "&& 1"
   [(const_int 0)]
 {
-  insn_code icode = code_for_pred_mulh (UNSPEC_VMULHS, mode);
-  riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
-  DONE;
-}
-[(set_attr "type" "vimul")])
-
-(define_insn_and_split "umul3_highpart"
-  [(set (match_operand:VFULLI 0 "register_operand")
-(umul_highpart:VFULLI
-  (match_operand:VFULLI 1 "register_operand")
-  (match_operand:VFULLI 2 "register_operand")))]
-  "TARGET_VECTOR && can_create_pseudo_p ()"
-  "#"
-  "&& 1"
-  [(const_int 0)]
-{
-  insn_code icode = code_for_pred_mulh (UNSPEC_VMULHU, mode);
+  insn_code icode = code_for_pred_mulh (, mode);
   riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
   DONE;
 }
diff --git a/gcc/config/riscv/vector-iterators.md 
b/gcc/config/riscv/vector-iterators.md
index 2f7f7cbe08c..e70a9bc5c74 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -2354,6 +2354,10 @@
 (define_code_iterator sat_int_plus_binop [ss_plus us_plus])
 (define_code_iterator sat_int_minus_binop [ss_minus us_minus])
 
+(define