Re: [PATCH] RISC-V: Support vundefine intrinsics for tuple types
LGTM.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-11-01 14:35
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH] RISC-V: Support vundefine intrinsics for tuple types
From: xuli
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/288
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-functions.def (vundefined): Add
vundefine intrinsics for tuple types.
* config/riscv/riscv-vector-builtins.cc: Ditto.
* config/riscv/vector.md (@vundefined): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/tuple_vundefined.c: New test.
---
.../riscv/riscv-vector-builtins-functions.def | 1 +
gcc/config/riscv/riscv-vector-builtins.cc | 8 ++
gcc/config/riscv/vector.md| 7 ++
.../riscv/rvv/base/tuple_vundefined.c | 73 +++
4 files changed, 89 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/tuple_vundefined.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 18ed2c2b8f6..911fd520195 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -622,6 +622,7 @@ DEF_RVV_FUNCTION (vget, vget, none_preds,
all_v_vget_lmul4_x2_ops)
DEF_RVV_FUNCTION (vset, vset, none_preds, all_v_vset_tuple_ops)
DEF_RVV_FUNCTION (vget, vget, none_preds, all_v_vget_tuple_ops)
DEF_RVV_FUNCTION (vcreate, vcreate, none_preds, all_v_vcreate_tuple_ops)
+DEF_RVV_FUNCTION (vundefined, vundefined, none_preds, all_none_void_tuple_ops)
DEF_RVV_FUNCTION (vlseg, seg_loadstore, full_preds,
tuple_v_scalar_const_ptr_ops)
DEF_RVV_FUNCTION (vsseg, seg_loadstore, none_m_preds, tuple_v_scalar_ptr_ops)
DEF_RVV_FUNCTION (vlsseg, seg_loadstore, full_preds,
tuple_v_scalar_const_ptr_ptrdiff_ops)
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
b/gcc/config/riscv/riscv-vector-builtins.cc
index 5d4dc264fa6..2e33bf73549 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -2509,6 +2509,14 @@ static CONSTEXPR const rvv_op_info
all_v_vcreate_tuple_ops
rvv_arg_type_info (RVV_BASE_vector), /* Return type */
tuple_vcreate_args /* Args */};
+/* A static operand information for vector_type func () function registration.
+ */
+static CONSTEXPR const rvv_op_info all_none_void_tuple_ops
+ = {tuple_ops, /* Types */
+ OP_TYPE_none, /* Suffix */
+ rvv_arg_type_info (RVV_BASE_vector), /* Return type */
+ void_args /* Args */};
+
/* A list of all RVV base function types. */
static CONSTEXPR const function_type_info function_types[] = {
#define DEF_RVV_TYPE_INDEX(\
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 0297e4f0227..35bb6c3dc58 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -880,6 +880,13 @@
""
[(set_attr "type" "vector")])
+(define_insn "@vundefined"
+ [(set (match_operand:VT 0 "register_operand" "=vr")
+ (unspec:VT [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]
+ "TARGET_VECTOR"
+ ""
+ [(set_attr "type" "vector")])
+
(define_expand "@vreinterpret"
[(set (match_operand:V 0 "register_operand")
(match_operand 1 "vector_any_register_operand"))]
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/tuple_vundefined.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple_vundefined.c
new file mode 100644
index 000..174860de559
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple_vundefined.c
@@ -0,0 +1,73 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+vfloat16mf4x2_t
+test_vundefined_f16mf4x2 ()
+{
+ return __riscv_vundefined_f16mf4x2 ();
+}
+
+vfloat32m1x3_t
+test_vundefined_f32m1x3 ()
+{
+ return __riscv_vundefined_f32m1x3 ();
+}
+
+vfloat64m1x5_t
+test_vundefined_f64m1x5 ()
+{
+ return __riscv_vundefined_f64m1x5 ();
+}
+
+vint8mf4x2_t
+test_vundefined_i8mf4x2 ()
+{
+ return __riscv_vundefined_i8mf4x2 ();
+}
+
+vint16mf4x8_t
+test_vundefined_i16mf4x8 ()
+{
+ return __riscv_vundefined_i16mf4x8 ();
+}
+
+vint32m1x7_t
+test_vundefined_i32m1x7 ()
+{
+ return __riscv_vundefined_i32m1x7 ();
+}
+
+vint64m1x4_t
+test_vundefined_i64m1x4 ()
+{
+ return __riscv_vundefined_i64m1x4 ();
+}
+
+vuint8mf8x2_t
+test_vundefined_u8mf8x2 ()
+{
+ return __riscv_vundefined_u8mf8x2 ();
+}
+
+vuint16mf4x4_t
+test_vundefined_u16mf4x4 ()
+{
+ return __riscv_vundefined_u16mf4x4 ();
+}
+
+vuint32m1x7_t
+test_vundefined_u32m1x7 ()
+{
+ return __riscv_vundefined_u32m1x7 ();
+}
+
+vuint64m4x2_t
+test_vundefined_u64m4x2 ()
+{
+ return __riscv_vundefined_u64m4x2 ();
+}
+
+/* { dg-final { scan-assembler-times {vse[0-9]+\.v\s+v[0-9]+,\s*0\([0-9ax]+\)}
18 } } */
+/* { dg-final { scan-assembler-times
{vs[0-9]+r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 28 } } */
--
2.17.1
[PATCH] RISC-V: Support vundefine intrinsics for tuple types
From: xuli
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/288
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-functions.def (vundefined): Add
vundefine intrinsics for tuple types.
* config/riscv/riscv-vector-builtins.cc: Ditto.
* config/riscv/vector.md (@vundefined): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/tuple_vundefined.c: New test.
---
.../riscv/riscv-vector-builtins-functions.def | 1 +
gcc/config/riscv/riscv-vector-builtins.cc | 8 ++
gcc/config/riscv/vector.md| 7 ++
.../riscv/rvv/base/tuple_vundefined.c | 73 +++
4 files changed, 89 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/tuple_vundefined.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 18ed2c2b8f6..911fd520195 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -622,6 +622,7 @@ DEF_RVV_FUNCTION (vget, vget, none_preds,
all_v_vget_lmul4_x2_ops)
DEF_RVV_FUNCTION (vset, vset, none_preds, all_v_vset_tuple_ops)
DEF_RVV_FUNCTION (vget, vget, none_preds, all_v_vget_tuple_ops)
DEF_RVV_FUNCTION (vcreate, vcreate, none_preds, all_v_vcreate_tuple_ops)
+DEF_RVV_FUNCTION (vundefined, vundefined, none_preds, all_none_void_tuple_ops)
DEF_RVV_FUNCTION (vlseg, seg_loadstore, full_preds,
tuple_v_scalar_const_ptr_ops)
DEF_RVV_FUNCTION (vsseg, seg_loadstore, none_m_preds, tuple_v_scalar_ptr_ops)
DEF_RVV_FUNCTION (vlsseg, seg_loadstore, full_preds,
tuple_v_scalar_const_ptr_ptrdiff_ops)
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
b/gcc/config/riscv/riscv-vector-builtins.cc
index 5d4dc264fa6..2e33bf73549 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -2509,6 +2509,14 @@ static CONSTEXPR const rvv_op_info
all_v_vcreate_tuple_ops
rvv_arg_type_info (RVV_BASE_vector), /* Return type */
tuple_vcreate_args /* Args */};
+/* A static operand information for vector_type func () function registration.
+ */
+static CONSTEXPR const rvv_op_info all_none_void_tuple_ops
+ = {tuple_ops, /* Types */
+ OP_TYPE_none, /* Suffix */
+ rvv_arg_type_info (RVV_BASE_vector), /* Return type */
+ void_args /* Args */};
+
/* A list of all RVV base function types. */
static CONSTEXPR const function_type_info function_types[] = {
#define DEF_RVV_TYPE_INDEX(
\
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 0297e4f0227..35bb6c3dc58 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -880,6 +880,13 @@
""
[(set_attr "type" "vector")])
+(define_insn "@vundefined"
+ [(set (match_operand:VT 0 "register_operand" "=vr")
+ (unspec:VT [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]
+ "TARGET_VECTOR"
+ ""
+ [(set_attr "type" "vector")])
+
(define_expand "@vreinterpret"
[(set (match_operand:V 0 "register_operand")
(match_operand 1 "vector_any_register_operand"))]
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/tuple_vundefined.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple_vundefined.c
new file mode 100644
index 000..174860de559
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple_vundefined.c
@@ -0,0 +1,73 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+vfloat16mf4x2_t
+test_vundefined_f16mf4x2 ()
+{
+ return __riscv_vundefined_f16mf4x2 ();
+}
+
+vfloat32m1x3_t
+test_vundefined_f32m1x3 ()
+{
+ return __riscv_vundefined_f32m1x3 ();
+}
+
+vfloat64m1x5_t
+test_vundefined_f64m1x5 ()
+{
+ return __riscv_vundefined_f64m1x5 ();
+}
+
+vint8mf4x2_t
+test_vundefined_i8mf4x2 ()
+{
+ return __riscv_vundefined_i8mf4x2 ();
+}
+
+vint16mf4x8_t
+test_vundefined_i16mf4x8 ()
+{
+ return __riscv_vundefined_i16mf4x8 ();
+}
+
+vint32m1x7_t
+test_vundefined_i32m1x7 ()
+{
+ return __riscv_vundefined_i32m1x7 ();
+}
+
+vint64m1x4_t
+test_vundefined_i64m1x4 ()
+{
+ return __riscv_vundefined_i64m1x4 ();
+}
+
+vuint8mf8x2_t
+test_vundefined_u8mf8x2 ()
+{
+ return __riscv_vundefined_u8mf8x2 ();
+}
+
+vuint16mf4x4_t
+test_vundefined_u16mf4x4 ()
+{
+ return __riscv_vundefined_u16mf4x4 ();
+}
+
+vuint32m1x7_t
+test_vundefined_u32m1x7 ()
+{
+ return __riscv_vundefined_u32m1x7 ();
+}
+
+vuint64m4x2_t
+test_vundefined_u64m4x2 ()
+{
+ return __riscv_vundefined_u64m4x2 ();
+}
+
+/* { dg-final { scan-assembler-times {vse[0-9]+\.v\s+v[0-9]+,\s*0\([0-9ax]+\)}
18 } } */
+/* { dg-final { scan-assembler-times
{vs[0-9]+r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 28 } } */
--
2.17.1
