subject:"\[PATCH\] RISC\-V\: Unify indention in riscv.md"

Re: [PATCH] RISC-V: Unify indention in riscv.md

2017-05-05 Thread Palmer Dabbelt

On Thu, 04 May 2017 05:40:29 PDT (-0700), Palmer Dabbelt wrote:
> From: Kito Cheng 
>
> This contains only whitespace changes.
>
> gcc/ChangeLog
>
> 2017-05-04  Kito Cheng  
>
>   * config/riscv/riscv.md: Unify indentation.
> ---
>  gcc/ChangeLog |   4 +
>  gcc/config/riscv/riscv.md | 559 
> --
>  2 files changed, 291 insertions(+), 272 deletions(-)
>
> diff --git a/gcc/ChangeLog b/gcc/ChangeLog
> index 8548845..fc85689 100644
> --- a/gcc/ChangeLog
> +++ b/gcc/ChangeLog
> @@ -1,3 +1,7 @@
> +2017-05-04  Kito Cheng  
> +
> + * config/riscv/riscv.md: Unify indentation.
> +
>  2017-05-04  Richard Sandiford  
>
>   * tree-ssa-loop-manip.c (niter_for_unrolled_loop): Add commentary
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 4cbb243..18dba3b 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -398,47 +398,47 @@
>  ;;
>
>  (define_insn "add3"
> -  [(set (match_operand:ANYF 0 "register_operand" "=f")
> - (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
> -(match_operand:ANYF 2 "register_operand" "f")))]
> +  [(set (match_operand:ANYF0 "register_operand" "=f")
> + (plus:ANYF (match_operand:ANYF 1 "register_operand" " f")
> +(match_operand:ANYF 2 "register_operand" " f")))]
>"TARGET_HARD_FLOAT"
>"fadd.\t%0,%1,%2"
>[(set_attr "type" "fadd")
> (set_attr "mode" "")])
>
>  (define_insn "addsi3"
> -  [(set (match_operand:SI 0 "register_operand" "=r,r")
> - (plus:SI (match_operand:SI 1 "register_operand" "r,r")
> -   (match_operand:SI 2 "arith_operand" "r,I")))]
> +  [(set (match_operand:SI  0 "register_operand" "=r,r")
> + (plus:SI (match_operand:SI 1 "register_operand" " r,r")
> +  (match_operand:SI 2 "arith_operand"" r,I")))]
>""
>{ return TARGET_64BIT ? "addw\t%0,%1,%2" : "add\t%0,%1,%2"; }
>[(set_attr "type" "arith")
> (set_attr "mode" "SI")])
>
>  (define_insn "adddi3"
> -  [(set (match_operand:DI 0 "register_operand" "=r,r")
> - (plus:DI (match_operand:DI 1 "register_operand" "r,r")
> -   (match_operand:DI 2 "arith_operand" "r,I")))]
> +  [(set (match_operand:DI  0 "register_operand" "=r,r")
> + (plus:DI (match_operand:DI 1 "register_operand" " r,r")
> +  (match_operand:DI 2 "arith_operand"" r,I")))]
>"TARGET_64BIT"
>"add\t%0,%1,%2"
>[(set_attr "type" "arith")
> (set_attr "mode" "DI")])
>
>  (define_insn "*addsi3_extended"
> -  [(set (match_operand:DI 0 "register_operand" "=r,r")
> +  [(set (match_operand:DI   0 "register_operand" "=r,r")
>   (sign_extend:DI
> -  (plus:SI (match_operand:SI 1 "register_operand" "r,r")
> -   (match_operand:SI 2 "arith_operand" "r,I"]
> +  (plus:SI (match_operand:SI 1 "register_operand" " r,r")
> +   (match_operand:SI 2 "arith_operand"" r,I"]
>"TARGET_64BIT"
>"addw\t%0,%1,%2"
>[(set_attr "type" "arith")
> (set_attr "mode" "SI")])
>
>  (define_insn "*addsi3_extended2"
> -  [(set (match_operand:DI 0 "register_operand" "=r,r")
> +  [(set (match_operand:DI   0 "register_operand" "=r,r")
>   (sign_extend:DI
> -   (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "r,r")
> -   (match_operand:DI 2 "arith_operand" "r,I"))
> +   (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" " r,r")
> +   (match_operand:DI 2 "arith_operand"" r,I"))
>0)))]
>"TARGET_64BIT"
>"addw\t%0,%1,%2"
> @@ -454,47 +454,47 @@
>  ;;
>
>  (define_insn "sub3"
> -  [(set (match_operand:ANYF 0 "register_operand" "=f")
> - (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
> - (match_operand:ANYF 2 "register_operand" "f")))]
> +  [(set (match_operand:ANYF 0 "register_operand" "=f")
> + (minus:ANYF (match_operand:ANYF 1 "register_operand" " f")
> + (match_operand:ANYF 2 "register_operand" " f")))]
>"TARGET_HARD_FLOAT"
>"fsub.\t%0,%1,%2"
>[(set_attr "type" "fadd")
> (set_attr "mode" "")])
>
>  (define_insn "subdi3"
> -  [(set (match_operand:DI 0 "register_operand" "=r")
> - (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
> -(match_operand:DI 2 "register_operand" "r")))]
> +  [(set (match_operand:DI 0"register_operand" "= r")
> + (minus:DI (match_operand:DI 1  "reg_or_0_operand" " rJ")
> +(match_operand:DI 2 "register_operand" "  r")))]
>"TARGET_64BIT"
>"sub\t%0,%z1,%2"
>[(set_attr "type" "arith")
> (set_attr "mode" "DI")])
>
>  (define_insn "subsi3"
> -  [(set (match_operand:SI 0 "register_operand" "=r")
> - (minus:SI (match_operand:SI 1

[PATCH] RISC-V: Unify indention in riscv.md

2017-05-04 Thread Palmer Dabbelt

From: Kito Cheng 

This contains only whitespace changes.

gcc/ChangeLog

2017-05-04  Kito Cheng  

* config/riscv/riscv.md: Unify indentation.
---
 gcc/ChangeLog |   4 +
 gcc/config/riscv/riscv.md | 559 --
 2 files changed, 291 insertions(+), 272 deletions(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 8548845..fc85689 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2017-05-04  Kito Cheng  
+
+   * config/riscv/riscv.md: Unify indentation.
+
 2017-05-04  Richard Sandiford  
 
* tree-ssa-loop-manip.c (niter_for_unrolled_loop): Add commentary
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 4cbb243..18dba3b 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -398,47 +398,47 @@
 ;;
 
 (define_insn "add3"
-  [(set (match_operand:ANYF 0 "register_operand" "=f")
-   (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
-  (match_operand:ANYF 2 "register_operand" "f")))]
+  [(set (match_operand:ANYF0 "register_operand" "=f")
+   (plus:ANYF (match_operand:ANYF 1 "register_operand" " f")
+  (match_operand:ANYF 2 "register_operand" " f")))]
   "TARGET_HARD_FLOAT"
   "fadd.\t%0,%1,%2"
   [(set_attr "type" "fadd")
(set_attr "mode" "")])
 
 (define_insn "addsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-   (plus:SI (match_operand:SI 1 "register_operand" "r,r")
- (match_operand:SI 2 "arith_operand" "r,I")))]
+  [(set (match_operand:SI  0 "register_operand" "=r,r")
+   (plus:SI (match_operand:SI 1 "register_operand" " r,r")
+(match_operand:SI 2 "arith_operand"" r,I")))]
   ""
   { return TARGET_64BIT ? "addw\t%0,%1,%2" : "add\t%0,%1,%2"; }
   [(set_attr "type" "arith")
(set_attr "mode" "SI")])
 
 (define_insn "adddi3"
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
-   (plus:DI (match_operand:DI 1 "register_operand" "r,r")
- (match_operand:DI 2 "arith_operand" "r,I")))]
+  [(set (match_operand:DI  0 "register_operand" "=r,r")
+   (plus:DI (match_operand:DI 1 "register_operand" " r,r")
+(match_operand:DI 2 "arith_operand"" r,I")))]
   "TARGET_64BIT"
   "add\t%0,%1,%2"
   [(set_attr "type" "arith")
(set_attr "mode" "DI")])
 
 (define_insn "*addsi3_extended"
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
+  [(set (match_operand:DI   0 "register_operand" "=r,r")
(sign_extend:DI
-(plus:SI (match_operand:SI 1 "register_operand" "r,r")
- (match_operand:SI 2 "arith_operand" "r,I"]
+(plus:SI (match_operand:SI 1 "register_operand" " r,r")
+ (match_operand:SI 2 "arith_operand"" r,I"]
   "TARGET_64BIT"
   "addw\t%0,%1,%2"
   [(set_attr "type" "arith")
(set_attr "mode" "SI")])
 
 (define_insn "*addsi3_extended2"
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
+  [(set (match_operand:DI   0 "register_operand" "=r,r")
(sign_extend:DI
- (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "r,r")
- (match_operand:DI 2 "arith_operand" "r,I"))
+ (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" " r,r")
+ (match_operand:DI 2 "arith_operand"" r,I"))
 0)))]
   "TARGET_64BIT"
   "addw\t%0,%1,%2"
@@ -454,47 +454,47 @@
 ;;
 
 (define_insn "sub3"
-  [(set (match_operand:ANYF 0 "register_operand" "=f")
-   (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
-   (match_operand:ANYF 2 "register_operand" "f")))]
+  [(set (match_operand:ANYF 0 "register_operand" "=f")
+   (minus:ANYF (match_operand:ANYF 1 "register_operand" " f")
+   (match_operand:ANYF 2 "register_operand" " f")))]
   "TARGET_HARD_FLOAT"
   "fsub.\t%0,%1,%2"
   [(set_attr "type" "fadd")
(set_attr "mode" "")])
 
 (define_insn "subdi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-   (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
-  (match_operand:DI 2 "register_operand" "r")))]
+  [(set (match_operand:DI 0"register_operand" "= r")
+   (minus:DI (match_operand:DI 1  "reg_or_0_operand" " rJ")
+  (match_operand:DI 2 "register_operand" "  r")))]
   "TARGET_64BIT"
   "sub\t%0,%z1,%2"
   [(set_attr "type" "arith")
(set_attr "mode" "DI")])
 
 (define_insn "subsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-   (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
-  (match_operand:SI 2 "register_operand" "r")))]
+  [(set (match_operand:SI   0 "register_operand" "= r")
+   (minus:SI (match_operand:SI 1 "reg_or_0_operand" " rJ")
+

Re: [PATCH] RISC-V: Unify indention in riscv.md

[PATCH] RISC-V: Unify indention in riscv.md

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