Hi,
As subject, this patch rewrites [su]mlal_high_n Neon intrinsics to use RTL
builtins rather than inline assembly code, allowing for better scheduling and
optimization.
Regression tested and bootstrapped on aarch64-none-linux-gnu and
aarch64_be-none-elf - no issues.
Ok for master?
Thanks,
Jonathan
--
gcc/ChangeLog:
2021-01-27 Jonathan Wright
* config/aarch64/aarch64-simd-builtins.def: Add [su]mlal_hi_n
builtin generator macros.
* config/aarch64/aarch64-simd.md (aarch64_mlal_hi_n_insn):
Define.
(aarch64_mlal_hi_n): Define.
* config/aarch64/arm_neon.h (vmlal_high_n_s16): Use RTL builtin
instead of inline asm.
(vmlal_high_n_s32): Likewise.
(vmlal_high_n_u16): Likewise.
(vmlal_high_n_u32): Likewise.
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index 2d91a0768d66fb8570ce518c06faae28c0ffcf27..c102289c26123ae913df87d327237647d2621655 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -234,6 +234,10 @@
BUILTIN_VQW (TERNOP, smlal_hi, 0, NONE)
BUILTIN_VQW (TERNOPU, umlal_hi, 0, NONE)
+ /* Implemented by aarch64_mlal_hi_n. */
+ BUILTIN_VQ_HSI (TERNOP, smlal_hi_n, 0, NONE)
+ BUILTIN_VQ_HSI (TERNOPU, umlal_hi_n, 0, NONE)
+
BUILTIN_VSQN_HSDI (UNOPUS, sqmovun, 0, NONE)
/* Implemented by aarch64_qmovn. */
BUILTIN_VSQN_HSDI (UNOP, sqmovn, 0, NONE)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index ff5037fb44ebb4d1d37ab838de6391e105e90bbf..a883f6ad4de8bb6d0c5f6478df5c516c159df4bb 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -1899,6 +1899,35 @@
}
)
+(define_insn "aarch64_mlal_hi_n_insn"
+ [(set (match_operand: 0 "register_operand" "=w")
+(plus:
+ (mult:
+ (ANY_EXTEND: (vec_select:
+ (match_operand:VQ_HSI 2 "register_operand" "w")
+ (match_operand:VQ_HSI 3 "vect_par_cnst_hi_half" "")))
+ (ANY_EXTEND: (vec_duplicate:
+ (match_operand: 4 "register_operand" ""
+ (match_operand: 1 "register_operand" "0")))]
+ "TARGET_SIMD"
+ "mlal2\t%0., %2., %4.[0]"
+ [(set_attr "type" "neon_mla__long")]
+)
+
+(define_expand "aarch64_mlal_hi_n"
+ [(match_operand: 0 "register_operand")
+ (match_operand: 1 "register_operand")
+ (ANY_EXTEND:(match_operand:VQ_HSI 2 "register_operand"))
+ (match_operand: 3 "register_operand")]
+ "TARGET_SIMD"
+{
+ rtx p = aarch64_simd_vect_par_cnst_half (mode, , true);
+ emit_insn (gen_aarch64_mlal_hi_n_insn (operands[0],
+ operands[1], operands[2], p, operands[3]));
+ DONE;
+}
+)
+
(define_insn "*aarch64_mlsl_lo"
[(set (match_operand: 0 "register_operand" "=w")
(minus:
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index 53aae934c37eadc179bb1d4e7fe033d06364628a..ae8526d5972067c05265a1f0bcf9fde5e347fb3b 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -7298,48 +7298,28 @@ __extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vmlal_high_n_s16 (int32x4_t __a, int16x8_t __b, int16_t __c)
{
- int32x4_t __result;
- __asm__ ("smlal2 %0.4s,%2.8h,%3.h[0]"
- : "=w"(__result)
- : "0"(__a), "w"(__b), "x"(__c)
- : /* No clobbers */);
- return __result;
+ return __builtin_aarch64_smlal_hi_nv8hi (__a, __b, __c);
}
__extension__ extern __inline int64x2_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vmlal_high_n_s32 (int64x2_t __a, int32x4_t __b, int32_t __c)
{
- int64x2_t __result;
- __asm__ ("smlal2 %0.2d,%2.4s,%3.s[0]"
- : "=w"(__result)
- : "0"(__a), "w"(__b), "w"(__c)
- : /* No clobbers */);
- return __result;
+ return __builtin_aarch64_smlal_hi_nv4si (__a, __b, __c);
}
__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vmlal_high_n_u16 (uint32x4_t __a, uint16x8_t __b, uint16_t __c)
{
- uint32x4_t __result;
- __asm__ ("umlal2 %0.4s,%2.8h,%3.h[0]"
- : "=w"(__result)
- : "0"(__a), "w"(__b), "x"(__c)
- : /* No clobbers */);
- return __result;
+ return __builtin_aarch64_umlal_hi_nv8hi_ (__a, __b, __c);
}
__extension__ extern __inline uint64x2_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vmlal_high_n_u32 (uint64x2_t __a, uint32x4_t __b, uint32_t __c)
{
- uint64x2_t __result;
- __asm__ ("umlal2 %0.2d,%2.4s,%3.s[0]"
- : "=w"(__result)
- : "0"(__a), "w"(__b), "w"(__c)
- : /* No clobbers */);
- return __result;
+ return __builtin_aarch64_umlal_hi_nv4si_ (__a, __b, __c);
}
__extension__ extern __inline int16x8_t
