Hello
This patch adds three extra builtins for the vectorized forms of the
abs, floorf and floor math functions, which are implemented by native
GCN instructions. I have also added a test to check that they generate
the expected assembler instructions.
Okay for trunk?
Thanks
KwokFrom 37f49b204d501327d0867b3e8a3f01b9445fb9bd Mon Sep 17 00:00:00 2001
From: Kwok Cheung Yeung
Date: Tue, 8 Nov 2022 11:59:58 +
Subject: [PATCH] amdgcn: Add builtins for vectorized native versions of abs,
floorf and floor
2022-11-08 Kwok Cheung Yeung
gcc/
* config/gcn/gcn-builtins.def (FABSV, FLOORVF, FLOORV): New builtins.
* config/gcn/gcn.cc (gcn_expand_builtin_1): Expand GCN_BUILTIN_FABSV,
GCN_BUILTIN_FLOORVF and GCN_BUILTIN_FLOORV.
gcc/testsuite/
* gcc.target/gcn/math-builtins-1.c: New test.
---
gcc/config/gcn/gcn-builtins.def | 15 +
gcc/config/gcn/gcn.cc | 33 +++
.../gcc.target/gcn/math-builtins-1.c | 33 +++
3 files changed, 81 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/gcn/math-builtins-1.c
diff --git a/gcc/config/gcn/gcn-builtins.def b/gcc/config/gcn/gcn-builtins.def
index 27691909925..c50777bd3b0 100644
--- a/gcc/config/gcn/gcn-builtins.def
+++ b/gcc/config/gcn/gcn-builtins.def
@@ -64,6 +64,21 @@ DEF_BUILTIN (FABSVF, 3 /*CODE_FOR_fabsvf */,
_A2 (GCN_BTI_V64SF, GCN_BTI_V64SF),
gcn_expand_builtin_1)
+DEF_BUILTIN (FABSV, 3 /*CODE_FOR_fabsv */,
+"fabsv", B_INSN,
+_A2 (GCN_BTI_V64DF, GCN_BTI_V64DF),
+gcn_expand_builtin_1)
+
+DEF_BUILTIN (FLOORVF, 3 /*CODE_FOR_floorvf */,
+"floorvf", B_INSN,
+_A2 (GCN_BTI_V64SF, GCN_BTI_V64SF),
+gcn_expand_builtin_1)
+
+DEF_BUILTIN (FLOORV, 3 /*CODE_FOR_floorv */,
+"floorv", B_INSN,
+_A2 (GCN_BTI_V64DF, GCN_BTI_V64DF),
+gcn_expand_builtin_1)
+
DEF_BUILTIN (LDEXPVF, 3 /*CODE_FOR_ldexpvf */,
"ldexpvf", B_INSN,
_A3 (GCN_BTI_V64SF, GCN_BTI_V64SF, GCN_BTI_V64SI),
diff --git a/gcc/config/gcn/gcn.cc b/gcc/config/gcn/gcn.cc
index 1996115a686..9c5e3419748 100644
--- a/gcc/config/gcn/gcn.cc
+++ b/gcc/config/gcn/gcn.cc
@@ -4329,6 +4329,39 @@ gcn_expand_builtin_1 (tree exp, rtx target, rtx
/*subtarget */ ,
emit_insn (gen_absv64sf2 (target, arg));
return target;
}
+case GCN_BUILTIN_FABSV:
+ {
+ if (ignore)
+ return target;
+ rtx arg = force_reg (V64DFmode,
+expand_expr (CALL_EXPR_ARG (exp, 0), NULL_RTX,
+ V64DFmode,
+ EXPAND_NORMAL));
+ emit_insn (gen_absv64df2 (target, arg));
+ return target;
+ }
+case GCN_BUILTIN_FLOORVF:
+ {
+ if (ignore)
+ return target;
+ rtx arg = force_reg (V64SFmode,
+expand_expr (CALL_EXPR_ARG (exp, 0), NULL_RTX,
+ V64SFmode,
+ EXPAND_NORMAL));
+ emit_insn (gen_floorv64sf2 (target, arg));
+ return target;
+ }
+case GCN_BUILTIN_FLOORV:
+ {
+ if (ignore)
+ return target;
+ rtx arg = force_reg (V64DFmode,
+expand_expr (CALL_EXPR_ARG (exp, 0), NULL_RTX,
+ V64DFmode,
+ EXPAND_NORMAL));
+ emit_insn (gen_floorv64df2 (target, arg));
+ return target;
+ }
case GCN_BUILTIN_LDEXPVF:
{
if (ignore)
diff --git a/gcc/testsuite/gcc.target/gcn/math-builtins-1.c
b/gcc/testsuite/gcc.target/gcn/math-builtins-1.c
new file mode 100644
index 000..e1aadfb40d9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/math-builtins-1.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-O1" } */
+
+typedef float v64sf __attribute__ ((vector_size (256)));
+typedef double v64df __attribute__ ((vector_size (512)));
+typedef int v64si __attribute__ ((vector_size (256)));
+typedef long v64di __attribute__ ((vector_size (512)));
+
+v64sf f (v64sf _x, v64si _y)
+{
+ v64sf x = _x;
+ v64si y = _y;
+ x = __builtin_gcn_fabsvf (x); /* { dg-final { scan-assembler
"v_add_f32\\s+v\[0-9\]+, 0, |v\[0-9\]+|" } } */
+ x = __builtin_gcn_floorvf (x); /* { dg-final { scan-assembler
"v_floor_f32\\s+v\[0-9\]+, v\[0-9\]+" } }*/
+ x = __builtin_gcn_frexpvf_mant (x); /* { dg-final { scan-assembler
"v_frexp_mant_f32\\s+v\[0-9\]+, v\[0-9\]+" } }*/
+ y = __builtin_gcn_frexpvf_exp (x); /* { dg-final { scan-assembler
"v_frexp_exp_i32_f32\\s+v\[0-9\]+, v\[0-9\]+" } }*/
+ x = __builtin_gcn_ldexpvf (x, y); /* { dg-final { scan-assembler
"v_ldexp_f32\\s+v\[0-9\]+, v\[0-9\]+, v\[0-9\]+&quo
