The CASE_VECTOR_SHORTEN_MODE query is missing some equals signs
which causes suboptimal codegen due to missed optimisation
opportunities. This patch also adds a test for thumb2
switch statements as none exist currently.
gcc/ChangeLog:
PR target/115353
* config/arm/arm.h (enum arm_auto_incmodes):
Correct CASE_VECTOR_SHORTEN_MODE query.
gcc/testsuite/ChangeLog:
* gcc.target/arm/thumb2-switchstatement.c: New test.diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 449e6935b32f8f272df709ba43aa2ba7de37e6b3..0cd5d733952d7620f452d9d90cec9103b3fb5300 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -2111,8 +2111,8 @@ enum arm_auto_incmodes
? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \
: SImode)\
: (TARGET_THUMB2 \
- ? ((min > 0 && max < 0x200) ? QImode\
- : (min > 0 && max <= 0x2) ? HImode\
+ ? ((min >= 0 && max < 0x200) ? QImode\
+ : (min >= 0 && max < 0x2) ? HImode\
: SImode)\
: ((min >= 0 && max < 1024) \
? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \
diff --git a/gcc/testsuite/gcc.target/arm/thumb2-switchstatement.c b/gcc/testsuite/gcc.target/arm/thumb2-switchstatement.c
new file mode 100644
index ..8badf318e626de1911e297bff8e93ac72160224f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/thumb2-switchstatement.c
@@ -0,0 +1,144 @@
+/* { dg-do compile } */
+/* { dg-options "-mthumb --param case-values-threshold=1 -fno-reorder-blocks -fno-tree-dce -O2" } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+#define NOP "nop;"
+#define NOP2 NOP NOP
+#define NOP4 NOP2 NOP2
+#define NOP8 NOP4 NOP4
+#define NOP16 NOP8 NOP8
+#define NOP32 NOP16 NOP16
+#define NOP64 NOP32 NOP32
+#define NOP128 NOP64 NOP64
+#define NOP256 NOP128 NOP128
+#define NOP512 NOP256 NOP256
+#define NOP1024 NOP512 NOP512
+#define NOP2048 NOP1024 NOP1024
+#define NOP4096 NOP2048 NOP2048
+#define NOP8192 NOP4096 NOP4096
+#define NOP16384 NOP8192 NOP8192
+#define NOP32768 NOP16384 NOP16384
+#define NOP65536 NOP32768 NOP32768
+#define NOP131072 NOP65536 NOP65536
+
+enum z
+{
+ a = 1,
+ b,
+ c,
+ d,
+ e,
+ f = 7,
+};
+
+inline void QIFunction (const char* flag)
+{
+ asm volatile (NOP32);
+ return;
+}
+
+inline void HIFunction (const char* flag)
+{
+ asm volatile (NOP512);
+ return;
+}
+
+inline void SIFunction (const char* flag)
+{
+ asm volatile (NOP131072);
+ return;
+}
+
+/*
+**QImode_test:
+** ...
+** tbb \[pc, r[0-9]+\]
+** ...
+*/
+__attribute__ ((noinline)) __attribute__ ((noclone)) const char* QImode_test(enum z x)
+{
+ switch (x)
+{
+ case d:
+QIFunction("QItest");
+return "InlineASM";
+ case f:
+return "TEST";
+ default:
+return "Default";
+}
+}
+
+/* { dg-final { scan-assembler ".byte" } } */
+
+/*
+**HImode_test:
+** ...
+** tbh \[pc, r[0-9]+, lsl #1\]
+** ...
+*/
+__attribute__ ((noinline)) __attribute__ ((noclone)) const char* HImode_test(enum z x)
+{
+ switch (x)
+ {
+case d:
+ HIFunction("HItest");
+ return "InlineASM";
+case f:
+ return "TEST";
+default:
+ return "Default";
+ }
+}
+
+/* { dg-final { scan-assembler ".2byte" } } */
+
+/*
+**SImode_test:
+** ...
+** adr (r[0-9]+), .L[0-9]+
+** ldr pc, \[\1, r[0-9]+, lsl #2\]
+** ...
+*/
+__attribute__ ((noinline)) __attribute__ ((noclone)) const char* SImode_test(enum z x)
+{
+ switch (x)
+ {
+case d:
+ SIFunction("SItest");
+ return "InlineASM";
+case f:
+ return "TEST";
+default:
+ return "Default";
+ }
+}
+
+/* { dg-final { scan-assembler ".word" } } */
+
+/*
+**backwards_branch_test:
+** ...
+** adr (r[0-9]+), .L[0-9]+
+** ldr pc, \[\1, r[0-9]+, lsl #2\]
+** ...
+*/
+__attribute__ ((noinline)) __attribute__ ((noclone)) const char* backwards_branch_test(enum z x, int flag)
+{
+ if (flag == 5)
+ {
+backwards:
+ asm volatile (NOP512);
+ return "ASM";
+ }
+ switch (x)
+ {
+case d:
+ goto backwards;
+case f:
+ return "TEST";
+default:
+ return "Default";
+ }
+}
\ No newline at end of file
