From: Christoph Müllner
The current support of the bitfield-extraction instructions
th.ext and th.extu (XTheadBb extension) only covers sign_extract
and zero_extract. This patch add support for sign_extend and
zero_extend to avoid any shifts for sign or zero extensions.
gcc/ChangeLog:
* config/riscv/riscv.md:
* config/riscv/thead.md (*extend2_th_ext):
(*zero_extendsidi2_th_extu):
(*zero_extendhi2_th_extu):
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xtheadbb-ext-1.c: New test.
* gcc.target/riscv/xtheadbb-extu-1.c: New test.
Signed-off-by: Christoph Müllner
---
gcc/config/riscv/riscv.md | 6 +-
gcc/config/riscv/thead.md | 31 +
.../gcc.target/riscv/xtheadbb-ext-1.c | 67 +++
.../gcc.target/riscv/xtheadbb-extu-1.c| 67 +++
4 files changed, 168 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 863400cd447..b763b84b763 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1368,7 +1368,7 @@ (define_insn_and_split "*zero_extendsidi2_internal"
[(set (match_operand:DI 0 "register_operand" "=r,r")
(zero_extend:DI
(match_operand:SI 1 "nonimmediate_operand" " r,m")))]
- "TARGET_64BIT && !TARGET_ZBA
+ "TARGET_64BIT && !TARGET_ZBA && !TARGET_XTHEADBB
&& !(REG_P (operands[1])
&& REGNO (operands[1]) == VL_REGNUM)"
"@
@@ -1395,7 +1395,7 @@ (define_insn_and_split "*zero_extendhi2"
[(set (match_operand:GPR0 "register_operand" "=r,r")
(zero_extend:GPR
(match_operand:HI 1 "nonimmediate_operand" " r,m")))]
- "!TARGET_ZBB"
+ "!TARGET_ZBB && !TARGET_XTHEADBB"
"@
#
lhu\t%0,%1"
@@ -1451,7 +1451,7 @@ (define_insn_and_split
"*extend2"
[(set (match_operand:SUPERQI 0 "register_operand" "=r,r")
(sign_extend:SUPERQI
(match_operand:SHORT 1 "nonimmediate_operand" " r,m")))]
- "!TARGET_ZBB"
+ "!TARGET_ZBB && !TARGET_XTHEADBB"
"@
#
l\t%0,%1"
diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
index 63c4af6f77d..978402e0b5d 100644
--- a/gcc/config/riscv/thead.md
+++ b/gcc/config/riscv/thead.md
@@ -59,6 +59,17 @@ (define_insn "*th_ext4"
[(set_attr "type" "bitmanip")
(set_attr "mode" "")])
+(define_insn "*extend2_th_ext"
+ [(set (match_operand:SUPERQI 0 "register_operand" "=r,r")
+ (sign_extend:SUPERQI
+ (match_operand:SHORT 1 "nonimmediate_operand" "r,m")))]
+ "TARGET_XTHEADBB"
+ "@
+ th.ext\t%0,%1,15,0
+ l\t%0,%1"
+ [(set_attr "type" "bitmanip,load")
+ (set_attr "mode" "")])
+
(define_insn "*th_extu4"
[(set (match_operand:GPR 0 "register_operand" "=r")
(zero_extract:GPR (match_operand:GPR 1 "register_operand" "r")
@@ -72,6 +83,26 @@ (define_insn "*th_extu4"
[(set_attr "type" "bitmanip")
(set_attr "mode" "")])
+(define_insn "*zero_extendsidi2_th_extu"
+ [(set (match_operand:DI 0 "register_operand" "=r,r")
+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")))]
+ "TARGET_64BIT && TARGET_XTHEADBB"
+ "@
+ th.extu\t%0,%1,31,0
+ lwu\t%0,%1"
+ [(set_attr "type" "bitmanip,load")
+ (set_attr "mode" "SI")])
+
+(define_insn "*zero_extendhi2_th_extu"
+ [(set (match_operand:GPR 0 "register_operand" "=r,r")
+ (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
+ "TARGET_XTHEADBB"
+ "@
+ th.extu\t%0,%1,15,0
+ lhu\t%0,%1"
+ [(set_attr "type" "bitmanip,load")
+ (set_attr "mode" "HI")])
+
(define_insn "*th_clz2"
[(set (match_operand:X 0 "register_operand" "=r")
(clz:X (match_operand:X 1 "register_operand" "r")))]
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c
b/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c
new file mode 100644
index 000..02f6ec1417d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c
@@ -0,0 +1,67 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xtheadbb" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_xtheadbb" { target { rv32 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */
+
+long sext64_32(int s32)
+{
+return s32;
+}
+
+long sext64_16(short s16)
+{
+return s16;
+}
+
+long sext64_8(char s8)
+{
+return s8;
+}
+
+int sext32_64(long s64)
+{
+return s64;
+}
+
+int sext32_16(short s16)
+{
+return s16;
+}
+
+int sext32_8(char s8)
+{
+return s8;
+}
+
+short sext16_64(long s64)
+{
+return s64;
+}
+
+short sext16_32(int s32)
+{
+return s32;
+}
+
+short sext16_8(char s8)
+{
+return s8;
+}
+
+char sext8_64(long s64)
+{
+return s64;
+}
+
+char sext8_32(int s32)
+{
+return s32;
+}
+
+char sext8_16(short s16)
+{
+return s16;
+}
+
+/* { dg-final { scan-assembler-not "slli" } } */
+/* { dg-fina
