Re: [PATCH 1/2] RISC-V: delete all the vector psabi checking.
../../gcc/config/riscv/riscv.cc: In function 'void riscv_init_cumulative_args(CUMULATIVE_ARGS*, tree, rtx, tree, int)': ../../gcc/config/riscv/riscv.cc:4879:34: error: unused parameter 'fndecl' [-Werror=unused-parameter] 4879 | tree fndecl, | ~^~ ../../gcc/config/riscv/riscv.cc: In function 'bool riscv_vector_mode_supported_any_target_p(machine_mode)': ../../gcc/config/riscv/riscv.cc:10537:56: error: unused parameter 'mode' [-Werror=unused-parameter] 10537 | riscv_vector_mode_supported_any_target_p (machine_mode mode) | ~^~~~ cc1plus: all warnings being treated as errors make[3]: *** [Makefile:2559: riscv.o] Error 1 -- Andreas Schwab, sch...@linux-m68k.org GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1 "And now for something completely different."
Re: [PATCH 1/2] RISC-V: delete all the vector psabi checking.
LGTM. I think removing riscv_vector_abi can be another separate followup patch.
But plz make sure you have passed the regression before committed.
Thanks.
juzhe.zh...@rivai.ai
From: yanzhang.wang
Date: 2024-01-15 14:00
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; lehua.ding; yanzhang.wang
Subject: [PATCH 1/2] RISC-V: delete all the vector psabi checking.
From: Yanzhang Wang
Thanks the
https://hub.fgit.cf/riscv-non-isa/riscv-elf-psabi-doc/pull/389, we
need not to maintain the psabi checking any more.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
(riscv_pass_in_vector_p): Delete.
(riscv_init_cumulative_args): Delete the checking.
(riscv_get_arg_info): Delete the checking.
(riscv_function_value): Delete the checking.
* config/riscv/riscv.h: Delete the member for checking.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/binop_vx_constraint-120.c: Delete the -Wno-psabi.
* gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c: Ditto.
* gcc.target/riscv/rvv/base/mask_insn_shortcut.c: Ditto.
* gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c: Ditto.
* gcc.target/riscv/rvv/base/pr110109-2.c: Ditto.
* gcc.target/riscv/rvv/base/scalar_move-9.c: Ditto.
* gcc.target/riscv/rvv/base/spill-10.c: Ditto.
* gcc.target/riscv/rvv/base/spill-11.c: Ditto.
* gcc.target/riscv/rvv/base/spill-9.c: Ditto.
* gcc.target/riscv/rvv/base/vlmul_ext-1.c: Ditto.
* gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c: Ditto.
* gcc.target/riscv/rvv/base/zvfh-intrinsic.c: Ditto.
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vsetvl-1.c: Ditto.
* gcc.target/riscv/rvv/base/vector-abi-1.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-2.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-3.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-4.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-5.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-6.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-7.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-8.c: Removed.
Signed-off-by: Yanzhang Wang
---
Have tested the two patches on my local and there's no regression.
---
gcc/config/riscv/riscv.cc | 80 +--
gcc/config/riscv/riscv.h | 2 -
.../riscv/rvv/base/binop_vx_constraint-120.c | 2 +-
.../rvv/base/integer_compare_insn_shortcut.c | 2 +-
.../riscv/rvv/base/mask_insn_shortcut.c | 2 +-
.../rvv/base/misc_vreinterpret_vbool_vint.c | 2 +-
.../gcc.target/riscv/rvv/base/pr110109-2.c| 2 +-
.../gcc.target/riscv/rvv/base/scalar_move-9.c | 2 +-
.../gcc.target/riscv/rvv/base/spill-10.c | 2 +-
.../gcc.target/riscv/rvv/base/spill-11.c | 2 +-
.../gcc.target/riscv/rvv/base/spill-9.c | 2 +-
.../gcc.target/riscv/rvv/base/vector-abi-1.c | 14
.../gcc.target/riscv/rvv/base/vector-abi-2.c | 15
.../gcc.target/riscv/rvv/base/vector-abi-3.c | 14
.../gcc.target/riscv/rvv/base/vector-abi-4.c | 16
.../gcc.target/riscv/rvv/base/vector-abi-5.c | 20 -
.../gcc.target/riscv/rvv/base/vector-abi-6.c | 20 -
.../gcc.target/riscv/rvv/base/vector-abi-7.c | 14
.../gcc.target/riscv/rvv/base/vector-abi-8.c | 14
.../gcc.target/riscv/rvv/base/vlmul_ext-1.c | 2 +-
.../base/zero_base_load_store_optimization.c | 2 +-
.../riscv/rvv/base/zvfh-intrinsic.c | 2 +-
.../riscv/rvv/base/zvfh-over-zvfhmin.c| 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-1.c| 2 +-
24 files changed, 15 insertions(+), 222 deletions(-)
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-1.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-2.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-3.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-4.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-5.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-6.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-7.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-8.c
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 32183d63180..e7f7ce605db 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4844,59 +4844,6 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1,
GEN_INT (offset2;
}
-/* Return true if a vector type is included in the type TYPE. */
-
-static bool
-riscv_arg_has_vector (const_tree type)
-{
- if (riscv_v_ext_mode_p (TYPE_MODE (type)))
-return true;
-
- if (!COMPLETE_TYPE_P (type))
-return false;
-
- switch (TREE_CODE (type))
-{
-case RECORD_TYPE:
- /* If it is a record, it is further determined whether its fields have
- vector type. */
- for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f))
- if (TREE_CODE (f) == FIELD_DECL)
- {
- tree field_type = TREE_TYPE (f);
- if (!T
Re: [PATCH 1/2] RISC-V: delete all the vector psabi checking.
I think you should also remove riscv_vector_abi
since vector ABI is ratified and we should by default enable vector calling
convention by default.
juzhe.zh...@rivai.ai
From: yanzhang.wang
Date: 2024-01-15 14:00
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; lehua.ding; yanzhang.wang
Subject: [PATCH 1/2] RISC-V: delete all the vector psabi checking.
From: Yanzhang Wang
Thanks the
https://hub.fgit.cf/riscv-non-isa/riscv-elf-psabi-doc/pull/389, we
need not to maintain the psabi checking any more.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
(riscv_pass_in_vector_p): Delete.
(riscv_init_cumulative_args): Delete the checking.
(riscv_get_arg_info): Delete the checking.
(riscv_function_value): Delete the checking.
* config/riscv/riscv.h: Delete the member for checking.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/binop_vx_constraint-120.c: Delete the -Wno-psabi.
* gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c: Ditto.
* gcc.target/riscv/rvv/base/mask_insn_shortcut.c: Ditto.
* gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c: Ditto.
* gcc.target/riscv/rvv/base/pr110109-2.c: Ditto.
* gcc.target/riscv/rvv/base/scalar_move-9.c: Ditto.
* gcc.target/riscv/rvv/base/spill-10.c: Ditto.
* gcc.target/riscv/rvv/base/spill-11.c: Ditto.
* gcc.target/riscv/rvv/base/spill-9.c: Ditto.
* gcc.target/riscv/rvv/base/vlmul_ext-1.c: Ditto.
* gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c: Ditto.
* gcc.target/riscv/rvv/base/zvfh-intrinsic.c: Ditto.
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vsetvl-1.c: Ditto.
* gcc.target/riscv/rvv/base/vector-abi-1.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-2.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-3.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-4.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-5.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-6.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-7.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-8.c: Removed.
Signed-off-by: Yanzhang Wang
---
Have tested the two patches on my local and there's no regression.
---
gcc/config/riscv/riscv.cc | 80 +--
gcc/config/riscv/riscv.h | 2 -
.../riscv/rvv/base/binop_vx_constraint-120.c | 2 +-
.../rvv/base/integer_compare_insn_shortcut.c | 2 +-
.../riscv/rvv/base/mask_insn_shortcut.c | 2 +-
.../rvv/base/misc_vreinterpret_vbool_vint.c | 2 +-
.../gcc.target/riscv/rvv/base/pr110109-2.c| 2 +-
.../gcc.target/riscv/rvv/base/scalar_move-9.c | 2 +-
.../gcc.target/riscv/rvv/base/spill-10.c | 2 +-
.../gcc.target/riscv/rvv/base/spill-11.c | 2 +-
.../gcc.target/riscv/rvv/base/spill-9.c | 2 +-
.../gcc.target/riscv/rvv/base/vector-abi-1.c | 14
.../gcc.target/riscv/rvv/base/vector-abi-2.c | 15
.../gcc.target/riscv/rvv/base/vector-abi-3.c | 14
.../gcc.target/riscv/rvv/base/vector-abi-4.c | 16
.../gcc.target/riscv/rvv/base/vector-abi-5.c | 20 -
.../gcc.target/riscv/rvv/base/vector-abi-6.c | 20 -
.../gcc.target/riscv/rvv/base/vector-abi-7.c | 14
.../gcc.target/riscv/rvv/base/vector-abi-8.c | 14
.../gcc.target/riscv/rvv/base/vlmul_ext-1.c | 2 +-
.../base/zero_base_load_store_optimization.c | 2 +-
.../riscv/rvv/base/zvfh-intrinsic.c | 2 +-
.../riscv/rvv/base/zvfh-over-zvfhmin.c| 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-1.c| 2 +-
24 files changed, 15 insertions(+), 222 deletions(-)
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-1.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-2.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-3.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-4.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-5.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-6.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-7.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-8.c
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 32183d63180..e7f7ce605db 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4844,59 +4844,6 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1,
GEN_INT (offset2;
}
-/* Return true if a vector type is included in the type TYPE. */
-
-static bool
-riscv_arg_has_vector (const_tree type)
-{
- if (riscv_v_ext_mode_p (TYPE_MODE (type)))
-return true;
-
- if (!COMPLETE_TYPE_P (type))
-return false;
-
- switch (TREE_CODE (type))
-{
-case RECORD_TYPE:
- /* If it is a record, it is further determined whether its fields have
- vector type. */
- for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f))
- if (TREE_CODE (f) == FIELD_DECL)
- {
- tree field_type = TREE_TYPE (f);
- if (!T
[PATCH 1/2] RISC-V: delete all the vector psabi checking.
From: Yanzhang Wang
Thanks the
https://hub.fgit.cf/riscv-non-isa/riscv-elf-psabi-doc/pull/389, we
need not to maintain the psabi checking any more.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
(riscv_pass_in_vector_p): Delete.
(riscv_init_cumulative_args): Delete the checking.
(riscv_get_arg_info): Delete the checking.
(riscv_function_value): Delete the checking.
* config/riscv/riscv.h: Delete the member for checking.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/binop_vx_constraint-120.c: Delete the
-Wno-psabi.
* gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c: Ditto.
* gcc.target/riscv/rvv/base/mask_insn_shortcut.c: Ditto.
* gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c: Ditto.
* gcc.target/riscv/rvv/base/pr110109-2.c: Ditto.
* gcc.target/riscv/rvv/base/scalar_move-9.c: Ditto.
* gcc.target/riscv/rvv/base/spill-10.c: Ditto.
* gcc.target/riscv/rvv/base/spill-11.c: Ditto.
* gcc.target/riscv/rvv/base/spill-9.c: Ditto.
* gcc.target/riscv/rvv/base/vlmul_ext-1.c: Ditto.
* gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c: Ditto.
* gcc.target/riscv/rvv/base/zvfh-intrinsic.c: Ditto.
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vsetvl-1.c: Ditto.
* gcc.target/riscv/rvv/base/vector-abi-1.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-2.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-3.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-4.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-5.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-6.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-7.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-8.c: Removed.
Signed-off-by: Yanzhang Wang
---
Have tested the two patches on my local and there's no regression.
---
gcc/config/riscv/riscv.cc | 80 +--
gcc/config/riscv/riscv.h | 2 -
.../riscv/rvv/base/binop_vx_constraint-120.c | 2 +-
.../rvv/base/integer_compare_insn_shortcut.c | 2 +-
.../riscv/rvv/base/mask_insn_shortcut.c | 2 +-
.../rvv/base/misc_vreinterpret_vbool_vint.c | 2 +-
.../gcc.target/riscv/rvv/base/pr110109-2.c| 2 +-
.../gcc.target/riscv/rvv/base/scalar_move-9.c | 2 +-
.../gcc.target/riscv/rvv/base/spill-10.c | 2 +-
.../gcc.target/riscv/rvv/base/spill-11.c | 2 +-
.../gcc.target/riscv/rvv/base/spill-9.c | 2 +-
.../gcc.target/riscv/rvv/base/vector-abi-1.c | 14
.../gcc.target/riscv/rvv/base/vector-abi-2.c | 15
.../gcc.target/riscv/rvv/base/vector-abi-3.c | 14
.../gcc.target/riscv/rvv/base/vector-abi-4.c | 16
.../gcc.target/riscv/rvv/base/vector-abi-5.c | 20 -
.../gcc.target/riscv/rvv/base/vector-abi-6.c | 20 -
.../gcc.target/riscv/rvv/base/vector-abi-7.c | 14
.../gcc.target/riscv/rvv/base/vector-abi-8.c | 14
.../gcc.target/riscv/rvv/base/vlmul_ext-1.c | 2 +-
.../base/zero_base_load_store_optimization.c | 2 +-
.../riscv/rvv/base/zvfh-intrinsic.c | 2 +-
.../riscv/rvv/base/zvfh-over-zvfhmin.c| 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-1.c| 2 +-
24 files changed, 15 insertions(+), 222 deletions(-)
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-1.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-2.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-3.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-4.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-5.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-6.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-7.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-8.c
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 32183d63180..e7f7ce605db 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4844,59 +4844,6 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1,
GEN_INT (offset2;
}
-/* Return true if a vector type is included in the type TYPE. */
-
-static bool
-riscv_arg_has_vector (const_tree type)
-{
- if (riscv_v_ext_mode_p (TYPE_MODE (type)))
-return true;
-
- if (!COMPLETE_TYPE_P (type))
-return false;
-
- switch (TREE_CODE (type))
-{
-case RECORD_TYPE:
- /* If it is a record, it is further determined whether its fields have
-vector type. */
- for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f))
- if (TREE_CODE (f) == FIELD_DECL)
- {
- tree field_type = TREE_TYPE (f);
- if (!TYPE_P (field_type))
- break;
-
- if (riscv_
