RE: [PATCH 1/2] arm: Add earlyclobber to MVE instructions that require it

[Kyrylo Tkachov]

Hi Andre,

> -Original Message-
> From: Andre Vieira (lists) 
> Sent: 23 March 2020 14:38
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov 
> Subject: [PATCH 1/2] arm: Add earlyclobber to MVE instructions that require
> it
> 
> 
> Hi,
> 
> This patch adds an earlyclobber to the MVE instructions that require it and
> were missing it. These are vrev64 and 32-bit element variants of vcadd,
> vhcadd vcmul, vmull[bt] and vqdmull[bt].
> 
> Regression tested on arm-none-eabi.
> 
> Is this OK for trunk?

Ok.
Thanks,
Kyrill

> 
> Cheers,
> Andre
> 
> 2020-03-23  Andre Vieira  
> 
>      * config/arm/mve.md (earlyclobber_32): New mode attribute.
>      (mve_vrev64q_*, mve_vcaddq*, mve_vhcaddq_*, mve_vcmulq_*,
>   mve_vmull[bt]q_*, mve_vqdmull[bt]q_*): Add appropriate early
> clobbers.

[PATCH 1/2] arm: Add earlyclobber to MVE instructions that require it

[Andre Vieira (lists)]

Hi,

This patch adds an earlyclobber to the MVE instructions that require it 
and were missing it. These are vrev64 and 32-bit element variants of 
vcadd, vhcadd vcmul, vmull[bt] and vqdmull[bt].


Regression tested on arm-none-eabi.

Is this OK for trunk?

Cheers,
Andre

2020-03-23  Andre Vieira  

    * config/arm/mve.md (earlyclobber_32): New mode attribute.
    (mve_vrev64q_*, mve_vcaddq*, mve_vhcaddq_*, mve_vcmulq_*,
 mve_vmull[bt]q_*, mve_vqdmull[bt]q_*): Add appropriate early 
clobbers.
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 
2e28d9d8408127dd52b9d16c772e7f27a47d390a..0cd67962a2641a3be46fe67819e093c0a712751b
 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -411,6 +411,8 @@ (define_mode_attr MVE_B_ELEM [ (V16QI "V16QI") (V8HI 
"V8QI") (V4SI "V4QI")])
 (define_mode_attr MVE_H_ELEM [ (V8HI "V8HI") (V4SI "V4HI")])
 (define_mode_attr V_sz_elem1 [(V16QI "b") (V8HI  "h") (V4SI "w") (V8HF "h")
  (V4SF "w")])
+(define_mode_attr earlyclobber_32 [(V16QI "=w") (V8HI "=w") (V4SI "=&w")
+   (V8HF "=w") (V4SF "=&w")])
 
 (define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U])
 (define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S])
@@ -856,7 +858,7 @@ (define_insn "mve_vrndaq_f"
 ;;
 (define_insn "mve_vrev64q_f"
   [
-   (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_0 0 "s_register_operand" "=&w")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
 VREV64Q_F))
   ]
@@ -967,7 +969,7 @@ (define_insn "mve_vcvtq_to_f_"
 ;;
 (define_insn "mve_vrev64q_"
   [
-   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_2 0 "s_register_operand" "=&w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
 VREV64Q))
   ]
@@ -1541,7 +1543,7 @@ (define_insn "mve_vbrsrq_n_"
 ;;
 (define_insn "mve_vcaddq_rot270_"
   [
-   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_2 0 "s_register_operand" "")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
   (match_operand:MVE_2 2 "s_register_operand" "w")]
 VCADDQ_ROT270))
@@ -1556,7 +1558,7 @@ (define_insn "mve_vcaddq_rot270_"
 ;;
 (define_insn "mve_vcaddq_rot90_"
   [
-   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_2 0 "s_register_operand" "")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
   (match_operand:MVE_2 2 "s_register_operand" "w")]
 VCADDQ_ROT90))
@@ -1841,7 +1843,7 @@ (define_insn "mve_vhaddq_"
 ;;
 (define_insn "mve_vhcaddq_rot270_s"
   [
-   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_2 0 "s_register_operand" "")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
   (match_operand:MVE_2 2 "s_register_operand" "w")]
 VHCADDQ_ROT270_S))
@@ -1856,7 +1858,7 @@ (define_insn "mve_vhcaddq_rot270_s"
 ;;
 (define_insn "mve_vhcaddq_rot90_s"
   [
-   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_2 0 "s_register_operand" "")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
   (match_operand:MVE_2 2 "s_register_operand" "w")]
 VHCADDQ_ROT90_S))
@@ -2096,7 +2098,7 @@ (define_insn "mve_vmulhq_"
 ;;
 (define_insn "mve_vmullbq_int_"
   [
-   (set (match_operand: 0 "s_register_operand" "=w")
+   (set (match_operand: 0 "s_register_operand" 
"")
(unspec: [(match_operand:MVE_2 1 "s_register_operand" 
"w")
  (match_operand:MVE_2 2 "s_register_operand" 
"w")]
 VMULLBQ_INT))
@@ -2111,7 +2113,7 @@ (define_insn "mve_vmullbq_int_"
 ;;
 (define_insn "mve_vmulltq_int_"
   [
-   (set (match_operand: 0 "s_register_operand" "=w")
+   (set (match_operand: 0 "s_register_operand" 
"")
(unspec: [(match_operand:MVE_2 1 "s_register_operand" 
"w")
  (match_operand:MVE_2 2 "s_register_operand" 
"w")]
 VMULLTQ_INT))
@@ -2621,7 +2623,7 @@ (define_insn "mve_vbicq_n_"
 ;;
 (define_insn "mve_vcaddq_rot270_f"
   [
-   (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_0 0 "s_register_operand" "")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
   (match_operand:MVE_0 2 "s_register_operand" "w")]
 VCADDQ_ROT270_F))
@@ -2636,7 +2638,7 @@ (define_insn "mve_vcaddq_rot270_f"
 ;;
 (define_insn "mve_vcaddq_rot90_f"
   [
-   (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_0 0 "s_register_operand" "")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
   (match_operand:MVE_0 2 "s_register_operand" "w")]
 VCADDQ_ROT90_F))
@@ -2831,7 +2833,7 @@ (define_insn "mve_vcmpneq_n