Re: [PATCH 2/2] Add IEEE 128-bit min/max support on PowerPC
On Wed, Apr 14, 2021 at 02:38:47PM -0500, Segher Boessenkool wrote: > On Fri, Apr 09, 2021 at 10:43:58AM -0400, Michael Meissner wrote: > > (Fv mode attribute): Add KFmode and TFmode. > > (movcc_fpmask): Replace > > movcc_p9. Add IEEE 128-bit fp support. > > (movcc_invert_fpmask): Replace > > movcc_invert_p9. Add IEEE 128-bit fp > > support. > > (fpmask): Add IEEE 128-bit fp support. Enable generator to > > build te RTL. > > (xxsel): Add IEEE 128-bit fp support. Enable generator to > > build te RTL. > > > @@ -608,8 +621,13 @@ (define_mode_attr Ff [(SF "f") (DF "d") (DI > > "d")]) > > ; SF/DF constraint for arithmetic on VSX registers using instructions > > added in > > ; ISA 2.06 (power7). This includes instructions that normally target DF > > mode, > > ; but are used on SFmode, since internally SFmode values are kept in the > > DFmode > > -; format. > > -(define_mode_attr Fv [(SF "wa") (DF "wa") (DI "wa")]) > > +; format. Also include IEEE 128-bit instructions which are restricted to > > the > > +; Altivec registers. > > +(define_mode_attr Fv [(SF "wa") > > +(DF "wa") > > +(DI "wa") > > +(KF "v") > > +(TF "v")]) > > Eww. Please just split the patterns. Fv should just go away, it is > always "wa" currently. Removing that cascades to more cleanups, which > is why I haven't done it yet, it takes time. The problem is you have a combinatorial explosion. Right now, there are two patterns, one for the normal move, and one for the inverted move. Without doing a cascaded combination, you would need some 32 patterns to cover all of the possibilities. Or you give up on having a conditional move that compares one type and moves a second: _Float128 a, b; double c, d, r; r = (a == b) ? c : d; As I recall when I put the original logic in, there were a few places that did this mixed comparison between SF/DF modes was used in real code. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meiss...@linux.ibm.com, phone: +1 (978) 899-4797
Re: [PATCH 2/2] Add IEEE 128-bit min/max support on PowerPC
On 14 April 2021 21:01:15 CEST, Segher Boessenkool
wrote:
>> > > --- /dev/null
>> > > +++ b/gcc/testsuite/gcc.target/powerpc/float128-cmove.c
>> > > @@ -0,0 +1,93 @@
>> > > +/* { dg-do compile } */
>> > > +/* { dg-require-effective-target ppc_float128_hw } */
>> > > +/* { dg-require-effective-target power10_ok } */
>> > > +/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
>> > > +/* { dg-final { scan-assembler {\mxscmpeq[dq]p\M} } } */
>> > > +/* { dg-final { scan-assembler {\mxxpermdi\M} } } */
>> > > +/* { dg-final { scan-assembler {\mxxsel\M}} } */
>> > > +/* { dg-final { scan-assembler-not {\mxscmpu[dq]p\M} } } */
>> > > +/* { dg-final { scan-assembler-not {\mfcmp[uo]\M} } } */
>> > > +/* { dg-final { scan-assembler-not {\mfsel\M} } } */
>>
>> I'd have expected scan-assembler-times fwiw.
>
>For what? scan-assembler-not *is* scan-assembler-times, in effect (but
>simpler of course, and it does work with capturing parens).
I meant -times for the occurrences of scan-assembler, not the -not, in case
that wasn't clear.
>Having too strict checks for generated code means no end to having to
>update many testcases when we have very small changes in the compiler.
>It's a balancing act. But maybe some -times would be good here, dunno.
>
>> > > +__float128
>> > > +eq_f128_d (__float128 a, __float128 b, double x, double y)
>> > > +{
>> > > + return (x != y) ? a : b;
>> > > +}
>>
>> I would think the above should be == since it's named eq_ and
>> the body would be redundant to ne_f128_d below as is.
>
>Good spot :-)
Well -times would maybe have caught exactly this I suppose.
I know the exact count can be cumbersome to maintain, but in this very specific
case which checks exactly the desired instruction it may be appropriate.
Just saying, prompted by the typo..
thanks,
Re: [PATCH 2/2] Add IEEE 128-bit min/max support on PowerPC
On Fri, Apr 09, 2021 at 10:43:58AM -0400, Michael Meissner wrote:
> (Fv mode attribute): Add KFmode and TFmode.
> (movcc_fpmask): Replace
> movcc_p9. Add IEEE 128-bit fp support.
> (movcc_invert_fpmask): Replace
> movcc_invert_p9. Add IEEE 128-bit fp
> support.
> (fpmask): Add IEEE 128-bit fp support. Enable generator to
> build te RTL.
> (xxsel): Add IEEE 128-bit fp support. Enable generator to
> build te RTL.
> @@ -608,8 +621,13 @@ (define_mode_attr Ff [(SF "f") (DF "d") (DI
> "d")])
> ; SF/DF constraint for arithmetic on VSX registers using instructions added
> in
> ; ISA 2.06 (power7). This includes instructions that normally target DF
> mode,
> ; but are used on SFmode, since internally SFmode values are kept in the
> DFmode
> -; format.
> -(define_mode_attr Fv [(SF "wa") (DF "wa") (DI "wa")])
> +; format. Also include IEEE 128-bit instructions which are restricted to the
> +; Altivec registers.
> +(define_mode_attr Fv [(SF "wa")
> + (DF "wa")
> + (DI "wa")
> + (KF "v")
> + (TF "v")])
Eww. Please just split the patterns. Fv should just go away, it is
always "wa" currently. Removing that cascades to more cleanups, which
is why I haven't done it yet, it takes time.
Almost all places that use Fv have no use at all for KF.
> (define_expand "movcc"
> - [(set (match_operand:SFDF 0 "gpc_reg_operand")
> - (if_then_else:SFDF (match_operand 1 "comparison_operator")
> - (match_operand:SFDF 2 "gpc_reg_operand")
> - (match_operand:SFDF 3 "gpc_reg_operand")))]
> + [(set (match_operand:FPMASK 0 "gpc_reg_operand")
> + (if_then_else:FPMASK (match_operand 1 "comparison_operator")
> + (match_operand:FPMASK 2 "gpc_reg_operand")
> + (match_operand:FPMASK 3 "gpc_reg_operand")))]
So you really want SFDFQF or such? That is much more generic than
"FPMASK", which doesn't explain what it means at all, either.
But, you can keep the patterns separate as well.
> - [(set_attr "length" "8")
> + ;; length is 12 in case we need to add XXPERMDI
> + [(set_attr "length" "12")
Which is only for QP. So really, just keep the patterns split.
> + return (FLOAT128_IEEE_P (mode)
> + ? "xscmp%V1qp %0,%2,%3"
> + : "xscmp%V1dp %x0,%x2,%x3");
Different output as well.
> -(define_insn "*xxsel"
> - [(set (match_operand:SFDF 0 "vsx_register_operand" "=")
> - (if_then_else:SFDF (ne (match_operand:V2DI 1 "vsx_register_operand"
> "wa")
> -(match_operand:V2DI 2 "zero_constant" ""))
> -(match_operand:SFDF 3 "vsx_register_operand" "")
> -(match_operand:SFDF 4 "vsx_register_operand"
> "")))]
> +(define_insn "xxsel"
> + [(set (match_operand:FPMASK 0 "vsx_register_operand" "=wa")
> + (if_then_else:FPMASK
> + (ne (match_operand:V2DI 1 "vsx_register_operand" "wa")
> + (match_operand:V2DI 2 "zero_constant" ""))
> + (match_operand:FPMASK 3 "vsx_register_operand" "wa")
> + (match_operand:FPMASK 4 "vsx_register_operand" "wa")))]
>"TARGET_P9_MINMAX"
>"xxsel %x0,%x4,%x3,%x1"
>[(set_attr "type" "vecmove")])
Please keep that a "*"; it should be generated via "movcc".
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/float128-cmove.c
> @@ -0,0 +1,93 @@
> +/* { dg-final { scan-assembler {\mxxsel\M}} } */
> +/* { dg-final { scan-assembler-not {\mfsel\M} } } */
It is somewhat problematic to require xxsel and disallow fsel (for one
thing, the compiler could always generated xxsel instead of any fsel).
But it will probably keep working fine, the routines here are very
short.
> +__float128
> +eq_f128_d (__float128 a, __float128 b, double x, double y)
> +{
> + return (x != y) ? a : b;
> +}
So "==" here.
Segher
Re: [PATCH 2/2] Add IEEE 128-bit min/max support on PowerPC
On Fri, Apr 09, 2021 at 09:20:32PM +0200, Bernhard Reutner-Fischer wrote:
> On Fri, 09 Apr 2021 11:54:59 -0500
> will schmidt via Gcc-patches wrote:
> > > + enum rtx_code cond = reverse_condition_maybe_unordered (GET_CODE
> > > (old_cmp));
>
> I think you can drop the enum keyword.
You can in C++, but not in C. It is fine to have it in C++ as well.
I think it is nicer in this case to lose the keyword, but it is hardly
harmful :-)
> > > --- /dev/null
> > > +++ b/gcc/testsuite/gcc.target/powerpc/float128-cmove.c
> > > @@ -0,0 +1,93 @@
> > > +/* { dg-do compile } */
> > > +/* { dg-require-effective-target ppc_float128_hw } */
> > > +/* { dg-require-effective-target power10_ok } */
> > > +/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
> > > +/* { dg-final { scan-assembler {\mxscmpeq[dq]p\M} } } */
> > > +/* { dg-final { scan-assembler {\mxxpermdi\M} } } */
> > > +/* { dg-final { scan-assembler {\mxxsel\M}} } */
> > > +/* { dg-final { scan-assembler-not {\mxscmpu[dq]p\M} } } */
> > > +/* { dg-final { scan-assembler-not {\mfcmp[uo]\M} } } */
> > > +/* { dg-final { scan-assembler-not {\mfsel\M} } } */
>
> I'd have expected scan-assembler-times fwiw.
For what? scan-assembler-not *is* scan-assembler-times, in effect (but
simpler of course, and it does work with capturing parens).
Having too strict checks for generated code means no end to having to
update many testcases when we have very small changes in the compiler.
It's a balancing act. But maybe some -times would be good here, dunno.
> > > +__float128
> > > +eq_f128_d (__float128 a, __float128 b, double x, double y)
> > > +{
> > > + return (x != y) ? a : b;
> > > +}
>
> I would think the above should be == since it's named eq_ and
> the body would be redundant to ne_f128_d below as is.
Good spot :-)
Segher
Re: [PATCH 2/2] Add IEEE 128-bit min/max support on PowerPC
On Fri, 09 Apr 2021 11:54:59 -0500
will schmidt via Gcc-patches wrote:
> On Fri, 2021-04-09 at 10:43 -0400, Michael Meissner wrote:
> > gcc/
> > 2021-04-09 Michael Meissner
> > (movcc_fpmask): Replace
> > movcc_p9. Add IEEE 128-bit fp support.
> > (movcc_invert_fpmask): Replace
> > movcc_invert_p9. Add IEEE 128-bit fp
> > support.
> > (fpmask): Add IEEE 128-bit fp support. Enable generator to
> > build te RTL.
> > (xxsel): Add IEEE 128-bit fp support. Enable generator to
> > build te RTL.
> ok
te? the?
> > diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
> > index 17b2fdc1cdd..ca4a4d01f05 100644
> > --- a/gcc/config/rs6000/rs6000.md
> > +++ b/gcc/config/rs6000/rs6000.md
> > ;; Handle inverting the fpmask comparisons.
> > -(define_insn_and_split "*movcc_invert_p9"
> > - [(set (match_operand:SFDF 0 "vsx_register_operand"
> > "=&,")
> > - (if_then_else:SFDF
> > +(define_insn_and_split "*movcc_invert_fpmask"
> > + [(set (match_operand:FPMASK 0 "vsx_register_operand" "=")
> > + (if_then_else:FPMASK
> > (match_operator:CCFP 1 "invert_fpmask_comparison_operator"
> > - [(match_operand:SFDF2 2 "vsx_register_operand"
> > ",")
> > -(match_operand:SFDF2 3 "vsx_register_operand"
> > ",")])
> > -(match_operand:SFDF 4 "vsx_register_operand" ",")
> > -(match_operand:SFDF 5 "vsx_register_operand" ",")))
> > - (clobber (match_scratch:V2DI 6 "=0,&wa"))]
> > + [(match_operand:FPMASK2 2 "vsx_register_operand" "")
> > +(match_operand:FPMASK2 3 "vsx_register_operand" "")])
> > +(match_operand:FPMASK 4 "vsx_register_operand" "")
> > +(match_operand:FPMASK 5 "vsx_register_operand" "")))
> > + (clobber (match_scratch:V2DI 6 "=&"))]
> >"TARGET_P9_MINMAX"
> >"#"
> >"&& 1"
> > - [(set (match_dup 6)
> > - (if_then_else:V2DI (match_dup 9)
> > - (match_dup 7)
> > - (match_dup 8)))
> > - (set (match_dup 0)
> > - (if_then_else:SFDF (ne (match_dup 6)
> > - (match_dup 8))
> > - (match_dup 5)
> > - (match_dup 4)))]
> > + [(pc)]
> > {
> > - rtx op1 = operands[1];
> > - enum rtx_code cond = reverse_condition_maybe_unordered (GET_CODE (op1));
> > + rtx dest = operands[0];
> > + rtx old_cmp = operands[1];
> > + rtx cmp_op1 = operands[2];
> > + rtx cmp_op2 = operands[3];
> > + enum rtx_code cond = reverse_condition_maybe_unordered (GET_CODE
> > (old_cmp));
I think you can drop the enum keyword.
Didn't read the pattern in detail.
> > + rtx cmp_rev = gen_rtx_fmt_ee (cond, CCFPmode, cmp_op1, cmp_op2);
> > + rtx move_f = operands[4];
> > + rtx move_t = operands[5];
> > + rtx mask_reg = operands[6];
> > + rtx mask_m1 = CONSTM1_RTX (V2DImode);
> > + rtx mask_0 = CONST0_RTX (V2DImode);
> > + machine_mode move_mode = mode;
> > + machine_mode compare_mode = mode;
> >
> > - if (GET_CODE (operands[6]) == SCRATCH)
> > -operands[6] = gen_reg_rtx (V2DImode);
> > + if (GET_CODE (mask_reg) == SCRATCH)
> > +mask_reg = gen_reg_rtx (V2DImode);
> >
> > - operands[7] = CONSTM1_RTX (V2DImode);
> > - operands[8] = CONST0_RTX (V2DImode);
> > + /* Emit the compare and set mask instruction. */
> > + emit_insn (gen_fpmask (mask_reg, cmp_rev, cmp_op1, cmp_op2,
> > + mask_m1, mask_0));
> >
> > - operands[9] = gen_rtx_fmt_ee (cond, CCFPmode, operands[2], operands[3]);
> > + /* If we have a 64-bit comparison, but an 128-bit move, we need to
> > extend the
> > + mask. Because we are using the splat builtin to extend the V2DImode,
> > we
> > + need to use element 1 on little endian systems. */
> > + if (!FLOAT128_IEEE_P (compare_mode) && FLOAT128_IEEE_P (move_mode))
> > +{
> > + rtx element = WORDS_BIG_ENDIAN ? const0_rtx : const1_rtx;
> > + emit_insn (gen_vsx_xxspltd_v2di (mask_reg, mask_reg, element));
> > +}
> > +
> > + /* Now emit the XXSEL insn. */
> > + emit_insn (gen_xxsel (dest, mask_reg, mask_0, move_t,
> > move_f));
> > + DONE;
> > }
> > - [(set_attr "length" "8")
> > + ;; length is 12 in case we need to add XXPERMDI
> > + [(set_attr "length" "12")
> >(set_attr "type" "vecperm")])
> >
> > -(define_insn "*fpmask"
> > - [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa")
> > +(define_insn "fpmask"
> > + [(set (match_operand:V2DI 0 "vsx_register_operand" "=")
> > (if_then_else:V2DI
> > (match_operator:CCFP 1 "fpmask_comparison_operator"
> > - [(match_operand:SFDF 2 "vsx_register_operand" "")
> > -(match_operand:SFDF 3 "vsx_register_operand" "")])
> > + [(match_operand:FPMASK 2 "vsx_register_operand" "")
> > +(match_operand:FPMASK 3 "vsx_register_operand" "")])
> > (match_operand:V2DI 4 "all_ones_constant" "")
> > (match_operand:V2DI 5 "zero_constant" "")))]
> >"TARGET_P9_MINMAX"
> >
Re: [PATCH 2/2] Add IEEE 128-bit min/max support on PowerPC
On Fri, 2021-04-09 at 10:43 -0400, Michael Meissner wrote:
> Add IEEE 128-bit fp conditional move on PowerPC.
>
> This patch has been posted various times in the past. My memory is the last
> time I changed the patch, I addressed the concerns posted at that time. Since
> then the patch seems to have gone into a limbo state.
This is covered in the patch series title page, Don't distract from the
patch itself here.
>
> This patch adds the support for power10 IEEE 128-bit floating point
> conditional
> move and for automatically generating min/max. Unlike the previous patch, I
> decided to keep two separate patterns for fpmask before splitting (one pattern
> for normal compares, and the other pattern for inverted compares). I can go
> back to a single pattern with a new predicate that allows either comparison.
ok.
>
> Compared to the original code, these patterns do simplify the fpmask insns to
> having one alternative instead of two. In the original code, the first
> alternative tried to use the result as a temporary register. But that doesn't
> work if you are doing a conditional move with SF/DF types, but the comparison
> is KF/TF. That is because the SF/DF types can use the traditional FPR
> registers, but IEEE 128-bit floating point can only do arithmetic in the
> traditional Altivec registers.
ok.
>
> This code also has to insert a XXPERMDI if you are moving KF/TF values, but
> the comparison is done with SF/DF values. In this case, the set and compare
> mask for SF/DF clears the bottom 64-bits of the register, and the XXPERMDI is
> needed to fill it.
ok.
>
> I have tested this patch in various little endian and big endian PowerPC
> builds
> since I've posted. It has no regressions, and it adds the instructions if
> -mcpu=power10 is used.
>
> gcc/
> 2021-04-09 Michael Meissner
>
> * config/rs6000/rs6000.c (have_compare_and_set_mask): Add IEEE
> 128-bit floating point types.
ok
> * config/rs6000/rs6000.md (FPMASK): New iterator.
> (FPMASK2): New iterator.
comment on this below.
> (Fv mode attribute): Add KFmode and TFmode.
ok
Missing an entry? I'm not certain I've followed changelog versus code
accurately here. May need an additional entry, stl
(movcc): Replace SFDF with FPMASK
> (movcc_fpmask): Replace
> movcc_p9. Add IEEE 128-bit fp support.
> (movcc_invert_fpmask): Replace
> movcc_invert_p9. Add IEEE 128-bit fp
> support.
> (fpmask): Add IEEE 128-bit fp support. Enable generator to
> build te RTL.
> (xxsel): Add IEEE 128-bit fp support. Enable generator to
> build te RTL.
ok
>
> gcc/testsuite/
> 2021-04-09 Michael Meissner
>
> * gcc.target/powerpc/float128-cmove.c: New test.
> * gcc.target/powerpc/float128-minmax-3.c: New test.
> ---
> gcc/config/rs6000/rs6000.c| 8 +-
> gcc/config/rs6000/rs6000.md | 186 --
> .../gcc.target/powerpc/float128-cmove.c | 93 +
> .../gcc.target/powerpc/float128-minmax-3.c| 15 ++
> 4 files changed, 236 insertions(+), 66 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/powerpc/float128-cmove.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/float128-minmax-3.c
>
> diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
> index e87686c1c4d..ad0d83f6d3f 100644
> --- a/gcc/config/rs6000/rs6000.c
> +++ b/gcc/config/rs6000/rs6000.c
> @@ -15706,8 +15706,8 @@ rs6000_emit_vector_cond_expr (rtx dest, rtx op_true,
> rtx op_false,
>return 1;
> }
>
> -/* Possibly emit the xsmaxcdp and xsmincdp instructions to emit a maximum or
> - minimum with "C" semantics.
> +/* Possibly emit the xsmaxc{dp,qp} and xsminc{dp,qp} instructions to emit a
> + maximum or minimum with "C" semantics.
>
> Unless you use -ffast-math, you can't use these instructions to replace
> conditions that implicitly reverse the condition because the comparison
> @@ -15843,6 +15843,10 @@ have_compare_and_set_mask (machine_mode mode)
> case E_DFmode:
>return TARGET_P9_MINMAX;
>
> +case E_KFmode:
> +case E_TFmode:
> + return FLOAT128_MIN_MAX_FPMASK_P (mode);
> +
> default:
>break;
> }
> diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
> index 17b2fdc1cdd..ca4a4d01f05 100644
> --- a/gcc/config/rs6000/rs6000.md
> +++ b/gcc/config/rs6000/rs6000.md
> @@ -575,6 +575,19 @@ (define_mode_iterator SFDF [SF DF])
> ; And again, for when we need two FP modes in a pattern.
> (define_mode_iterator SFDF2 [SF DF])
>
> +; Floating scalars that supports the set compare mask instruction.
> +(define_mode_iterator FPMASK [SF
> + DF
> + (KF "FLOAT128_MIN_MAX_FPMASK_P (KFmode)")
> + (TF "FLOAT128_MIN_MAX_FPMASK_P (TFmode)")])
> +
> +; And again, for patterns that need two (potentially) di
[PATCH 2/2] Add IEEE 128-bit min/max support on PowerPC
Add IEEE 128-bit fp conditional move on PowerPC.
This patch has been posted various times in the past. My memory is the last
time I changed the patch, I addressed the concerns posted at that time. Since
then the patch seems to have gone into a limbo state.
This patch adds the support for power10 IEEE 128-bit floating point conditional
move and for automatically generating min/max. Unlike the previous patch, I
decided to keep two separate patterns for fpmask before splitting (one pattern
for normal compares, and the other pattern for inverted compares). I can go
back to a single pattern with a new predicate that allows either comparison.
Compared to the original code, these patterns do simplify the fpmask insns to
having one alternative instead of two. In the original code, the first
alternative tried to use the result as a temporary register. But that doesn't
work if you are doing a conditional move with SF/DF types, but the comparison
is KF/TF. That is because the SF/DF types can use the traditional FPR
registers, but IEEE 128-bit floating point can only do arithmetic in the
traditional Altivec registers.
This code also has to insert a XXPERMDI if you are moving KF/TF values, but
the comparison is done with SF/DF values. In this case, the set and compare
mask for SF/DF clears the bottom 64-bits of the register, and the XXPERMDI is
needed to fill it.
I have tested this patch in various little endian and big endian PowerPC builds
since I've posted. It has no regressions, and it adds the instructions if
-mcpu=power10 is used.
gcc/
2021-04-09 Michael Meissner
* config/rs6000/rs6000.c (have_compare_and_set_mask): Add IEEE
128-bit floating point types.
* config/rs6000/rs6000.md (FPMASK): New iterator.
(FPMASK2): New iterator.
(Fv mode attribute): Add KFmode and TFmode.
(movcc_fpmask): Replace
movcc_p9. Add IEEE 128-bit fp support.
(movcc_invert_fpmask): Replace
movcc_invert_p9. Add IEEE 128-bit fp
support.
(fpmask): Add IEEE 128-bit fp support. Enable generator to
build te RTL.
(xxsel): Add IEEE 128-bit fp support. Enable generator to
build te RTL.
gcc/testsuite/
2021-04-09 Michael Meissner
* gcc.target/powerpc/float128-cmove.c: New test.
* gcc.target/powerpc/float128-minmax-3.c: New test.
---
gcc/config/rs6000/rs6000.c| 8 +-
gcc/config/rs6000/rs6000.md | 186 --
.../gcc.target/powerpc/float128-cmove.c | 93 +
.../gcc.target/powerpc/float128-minmax-3.c| 15 ++
4 files changed, 236 insertions(+), 66 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/powerpc/float128-cmove.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/float128-minmax-3.c
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index e87686c1c4d..ad0d83f6d3f 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -15706,8 +15706,8 @@ rs6000_emit_vector_cond_expr (rtx dest, rtx op_true,
rtx op_false,
return 1;
}
-/* Possibly emit the xsmaxcdp and xsmincdp instructions to emit a maximum or
- minimum with "C" semantics.
+/* Possibly emit the xsmaxc{dp,qp} and xsminc{dp,qp} instructions to emit a
+ maximum or minimum with "C" semantics.
Unless you use -ffast-math, you can't use these instructions to replace
conditions that implicitly reverse the condition because the comparison
@@ -15843,6 +15843,10 @@ have_compare_and_set_mask (machine_mode mode)
case E_DFmode:
return TARGET_P9_MINMAX;
+case E_KFmode:
+case E_TFmode:
+ return FLOAT128_MIN_MAX_FPMASK_P (mode);
+
default:
break;
}
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 17b2fdc1cdd..ca4a4d01f05 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -575,6 +575,19 @@ (define_mode_iterator SFDF [SF DF])
; And again, for when we need two FP modes in a pattern.
(define_mode_iterator SFDF2 [SF DF])
+; Floating scalars that supports the set compare mask instruction.
+(define_mode_iterator FPMASK [SF
+ DF
+ (KF "FLOAT128_MIN_MAX_FPMASK_P (KFmode)")
+ (TF "FLOAT128_MIN_MAX_FPMASK_P (TFmode)")])
+
+; And again, for patterns that need two (potentially) different floating point
+; scalars that support the set compare mask instruction.
+(define_mode_iterator FPMASK2 [SF
+ DF
+ (KF "FLOAT128_MIN_MAX_FPMASK_P (KFmode)")
+ (TF "FLOAT128_MIN_MAX_FPMASK_P (TFmode)")])
+
; A generic s/d attribute, for sp/dp for example.
(define_mode_attr sd [(SF "s") (DF "d")
(V4SF "s") (V2DF "d")])
@@ -608,8 +621,13 @@ (define_mode_attr Ff [(SF "f") (DF "d") (DI
"d")])
; SF/DF constraint for arithmetic on VSX registers u
