Hi,
For those fixed point <-> floating point vector conversion with
same element unit size, such as: SP <-> SI, DP <-> DI, it's fine
to use the existing RTL operations like any_fix/any_float for them.
This patch is to update them with any_fix/any_float.
Bootstrapped and regress tested on powerpc64le-linux-gnu.
gcc/ChangeLog
2019-10-23 Kewen Lin
* config/rs6000/vsx.md (UNSPEC_VSX_CV[SU]XWSP,
UNSPEC_VSX_XVCV[SU]XDDP, UNSPEC_VSX_XVCVDP[SU]XDS,
UNSPEC_VSX_XVCVSPSXWS): Remove.
(vsx_xvcv[su]xddp, vsx_xvcvdp[su]xds, vsx_xvcvsp[su]xws,
vsx_xvcv[su]xwsp): Update define_insn RTL patterns.
>From 39ae875d4ae6ce22e170aeb456ef307a1f5fd1e0 Mon Sep 17 00:00:00 2001
From: Kewen Lin
Date: Wed, 23 Oct 2019 02:56:48 -0500
Subject: [PATCH 2/3] Update RTL pattern on vector SP<->[SU]W DP<->[SU]D
conversion
---
gcc/config/rs6000/vsx.md | 105 +--
1 file changed, 28 insertions(+), 77 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index d6f079c..83e4071 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -277,8 +277,6 @@
UNSPEC_VSX_CVUXDSP
UNSPEC_VSX_CVSPSXDS
UNSPEC_VSX_CVSPUXDS
- UNSPEC_VSX_CVSXWSP
- UNSPEC_VSX_CVUXWSP
UNSPEC_VSX_FLOAT2
UNSPEC_VSX_UNS_FLOAT2
UNSPEC_VSX_FLOATE
@@ -298,12 +296,7 @@
UNSPEC_VSX_DIVSD
UNSPEC_VSX_DIVUD
UNSPEC_VSX_MULSD
- UNSPEC_VSX_XVCVSXDDP
- UNSPEC_VSX_XVCVUXDDP
- UNSPEC_VSX_XVCVDPSXDS
- UNSPEC_VSX_XVCVDPUXDS
UNSPEC_VSX_SIGN_EXTEND
- UNSPEC_VSX_XVCVSPSXWS
UNSPEC_VSX_XVCVSPSXDS
UNSPEC_VSX_VSLO
UNSPEC_VSX_EXTRACT
@@ -2202,6 +2195,34 @@
;; Convert and scale (used by vec_ctf, vec_cts, vec_ctu for double/long long)
+(define_insn "vsx_xvcvxwsp"
+ [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
+ (any_float:V4SF (match_operand:V4SI 1 "vsx_register_operand" "wa")))]
+ "VECTOR_UNIT_VSX_P (V4SFmode)"
+ "xvcvxwsp %x0,%x1"
+ [(set_attr "type" "vecfloat")])
+
+(define_insn "vsx_xvcvxddp"
+ [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa")
+(any_float:V2DF (match_operand:V2DI 1 "vsx_register_operand" "wa")))]
+ "VECTOR_UNIT_VSX_P (V2DFmode)"
+ "xvcvxddp %x0,%x1"
+ [(set_attr "type" "vecdouble")])
+
+(define_insn "vsx_xvcvspxws"
+ [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa")
+(any_fix:V4SI (match_operand:V4SF 1 "vsx_register_operand" "wa")))]
+ "VECTOR_UNIT_VSX_P (V4SFmode)"
+ "xvcvspxws %x0,%x1"
+ [(set_attr "type" "vecfloat")])
+
+(define_insn "vsx_xvcvdpxds"
+ [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa")
+(any_fix:V2DI (match_operand:V2DF 1 "vsx_register_operand" "wa")))]
+ "VECTOR_UNIT_VSX_P (V2DFmode)"
+ "xvcvdpxds %x0,%x1"
+ [(set_attr "type" "vecdouble")])
+
(define_expand "vsx_xvcvsxddp_scale"
[(match_operand:V2DF 0 "vsx_register_operand")
(match_operand:V2DI 1 "vsx_register_operand")
@@ -2217,14 +2238,6 @@
DONE;
})
-(define_insn "vsx_xvcvsxddp"
- [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa")
-(unspec:V2DF [(match_operand:V2DI 1 "vsx_register_operand" "wa")]
- UNSPEC_VSX_XVCVSXDDP))]
- "VECTOR_UNIT_VSX_P (V2DFmode)"
- "xvcvsxddp %x0,%x1"
- [(set_attr "type" "vecdouble")])
-
(define_expand "vsx_xvcvuxddp_scale"
[(match_operand:V2DF 0 "vsx_register_operand")
(match_operand:V2DI 1 "vsx_register_operand")
@@ -2240,14 +2253,6 @@
DONE;
})
-(define_insn "vsx_xvcvuxddp"
- [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa")
-(unspec:V2DF [(match_operand:V2DI 1 "vsx_register_operand" "wa")]
- UNSPEC_VSX_XVCVUXDDP))]
- "VECTOR_UNIT_VSX_P (V2DFmode)"
- "xvcvuxddp %x0,%x1"
- [(set_attr "type" "vecdouble")])
-
(define_expand "vsx_xvcvdpsxds_scale"
[(match_operand:V2DI 0 "vsx_register_operand")
(match_operand:V2DF 1 "vsx_register_operand")
@@ -2270,26 +2275,6 @@
})
;; convert vector of 64-bit floating point numbers to vector of
-;; 64-bit signed integer
-(define_insn "vsx_xvcvdpsxds"
- [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa")
-(unspec:V2DI [(match_operand:V2DF 1 "vsx_register_operand" "wa")]
- UNSPEC_VSX_XVCVDPSXDS))]
- "VECTOR_UNIT_VSX_P (V2DFmode)"
- "xvcvdpsxds %x0,%x1"
- [(set_attr "type" "vecdouble")])
-
-;; convert vector of 32-bit floating point numbers to vector of
-;; 32-bit signed integer
-(define_insn "vsx_xvcvspsxws"
- [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa")
- (unspec:V4SI [(match_operand:V4SF 1 "vsx_register_operand" "wa")]
-UNSPEC_VSX_XVCVSPSXWS))]
- "VECTOR_UNIT_VSX_P (V4SFmode)"
- "xvcvspsxws %x0,%x1"
- [(set_attr "type" "vecfloat")])
-
-;; convert vector of 64-bit floating point numbers to vector of
;; 64-bit unsigned integer
(define_expand "vsx_xvcvdpuxds_scale"
[(match_operand:V2DI 0 "vsx_register_operand")
@@ -2312,24 +2297,6 @@
DONE;
})
-;; convert vector of 32-bit
