Re: [PATCH 3/7] arm: Auto-vectorization for MVE: veor
LGTM, but please wait for maintainer review. On 25/11/2020 13:54, Christophe Lyon via Gcc-patches wrote: This patch enables MVE veorq instructions for auto-vectorization. MVE veorq insns in mve.md are modified to use xor instead of unspec expression to support xor3. The xor3 expander is added to vec-common.md 2020-11-12 Christophe Lyon gcc/ * config/arm/iterators.md (supf): Remove VEORQ_S and VEORQ_U. (VEORQ): Remove. * config/arm/mve.md (mve_veorq_u): New entry for veor instruction using expression xor. (mve_veorq_s): New expander. * config/arm/neon.md (xor3): Renamed into xor3_neon. * config/arm/unspscs.md (VEORQ_S, VEORQ_U): Remove. * config/arm/vec-common.md (xor3): New expander. gcc/testsuite/ * gcc.target/arm/simd/mve-veor.c: Add tests for veor. --- gcc/config/arm/iterators.md | 3 +-- gcc/config/arm/mve.md| 17 ++ gcc/config/arm/neon.md | 2 +- gcc/config/arm/unspecs.md| 2 -- gcc/config/arm/vec-common.md | 15 gcc/testsuite/gcc.target/arm/simd/mve-veor.c | 34 6 files changed, 63 insertions(+), 10 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-veor.c diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 5fcb7af..0195275 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -1237,7 +1237,7 @@ (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s") (VCADDQ_ROT270_U "u") (VCADDQ_ROT90_S "s") (VCMPEQQ_S "s") (VCMPEQQ_U "u") (VCADDQ_ROT90_U "u") (VCMPEQQ_N_S "s") (VCMPEQQ_N_U "u") (VCMPNEQ_N_S "s") - (VCMPNEQ_N_U "u") (VEORQ_S "s") (VEORQ_U "u") + (VCMPNEQ_N_U "u") (VHADDQ_N_S "s") (VHADDQ_N_U "u") (VHADDQ_S "s") (VHADDQ_U "u") (VHSUBQ_N_S "s") (VHSUBQ_N_U "u") (VHSUBQ_S "s") (VMAXQ_S "s") (VMAXQ_U "u") (VHSUBQ_U "u") @@ -1507,7 +1507,6 @@ (define_int_iterator VCADDQ_ROT90 [VCADDQ_ROT90_U VCADDQ_ROT90_S]) (define_int_iterator VCMPEQQ [VCMPEQQ_U VCMPEQQ_S]) (define_int_iterator VCMPEQQ_N [VCMPEQQ_N_S VCMPEQQ_N_U]) (define_int_iterator VCMPNEQ_N [VCMPNEQ_N_U VCMPNEQ_N_S]) -(define_int_iterator VEORQ [VEORQ_U VEORQ_S]) (define_int_iterator VHADDQ [VHADDQ_S VHADDQ_U]) (define_int_iterator VHADDQ_N [VHADDQ_N_U VHADDQ_N_S]) (define_int_iterator VHSUBQ [VHSUBQ_S VHSUBQ_U]) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 0f04044..a5f5d75 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -1204,17 +1204,24 @@ (define_insn "mve_vcmpneq_n_" ;; ;; [veorq_u, veorq_s]) ;; -(define_insn "mve_veorq_" +(define_insn "mve_veorq_u" [ (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w")] -VEORQ)) + (xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE" - "veor %q0, %q1, %q2" + "veor\t%q0, %q1, %q2" [(set_attr "type" "mve_move") ]) +(define_expand "mve_veorq_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand") + (xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand") + (match_operand:MVE_2 2 "s_register_operand"))) + ] + "TARGET_HAVE_MVE" +) ;; ;; [vhaddq_n_u, vhaddq_n_s]) diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 669c34d..e1263b0 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -747,7 +747,7 @@ (define_insn "bic3_neon" [(set_attr "type" "neon_logic")] ) -(define_insn "xor3" +(define_insn "xor3_neon" [(set (match_operand:VDQ 0 "s_register_operand" "=w") (xor:VDQ (match_operand:VDQ 1 "s_register_operand" "w") (match_operand:VDQ 2 "s_register_operand" "w")))] diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index f111ad8..78313ea 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -608,7 +608,6 @@ (define_c_enum "unspec" [ VCMPEQQ_S VCMPEQQ_N_S VCMPNEQ_N_S - VEORQ_S VHADDQ_S VHADDQ_N_S VHSUBQ_S @@ -653,7 +652,6 @@ (define_c_enum "unspec" [ VCMPEQQ_U VCMPEQQ_N_U VCMPNEQ_N_U - VEORQ_U VHADDQ_U VHADDQ_N_U VHSUBQ_U diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index 413fb07..687134a 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -202,3 +202,18 @@ (define_expand "ior3" (match_operand:VNINOTM1 2 "neon_logic_op2" "")))] "TARGET_NEON" ) + +(define_expand "xor3" + [(set (
[PATCH 3/7] arm: Auto-vectorization for MVE: veor
This patch enables MVE veorq instructions for auto-vectorization. MVE veorq insns in mve.md are modified to use xor instead of unspec expression to support xor3. The xor3 expander is added to vec-common.md 2020-11-12 Christophe Lyon gcc/ * config/arm/iterators.md (supf): Remove VEORQ_S and VEORQ_U. (VEORQ): Remove. * config/arm/mve.md (mve_veorq_u): New entry for veor instruction using expression xor. (mve_veorq_s): New expander. * config/arm/neon.md (xor3): Renamed into xor3_neon. * config/arm/unspscs.md (VEORQ_S, VEORQ_U): Remove. * config/arm/vec-common.md (xor3): New expander. gcc/testsuite/ * gcc.target/arm/simd/mve-veor.c: Add tests for veor. --- gcc/config/arm/iterators.md | 3 +-- gcc/config/arm/mve.md| 17 ++ gcc/config/arm/neon.md | 2 +- gcc/config/arm/unspecs.md| 2 -- gcc/config/arm/vec-common.md | 15 gcc/testsuite/gcc.target/arm/simd/mve-veor.c | 34 6 files changed, 63 insertions(+), 10 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-veor.c diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 5fcb7af..0195275 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -1237,7 +1237,7 @@ (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s") (VCADDQ_ROT270_U "u") (VCADDQ_ROT90_S "s") (VCMPEQQ_S "s") (VCMPEQQ_U "u") (VCADDQ_ROT90_U "u") (VCMPEQQ_N_S "s") (VCMPEQQ_N_U "u") (VCMPNEQ_N_S "s") - (VCMPNEQ_N_U "u") (VEORQ_S "s") (VEORQ_U "u") + (VCMPNEQ_N_U "u") (VHADDQ_N_S "s") (VHADDQ_N_U "u") (VHADDQ_S "s") (VHADDQ_U "u") (VHSUBQ_N_S "s") (VHSUBQ_N_U "u") (VHSUBQ_S "s") (VMAXQ_S "s") (VMAXQ_U "u") (VHSUBQ_U "u") @@ -1507,7 +1507,6 @@ (define_int_iterator VCADDQ_ROT90 [VCADDQ_ROT90_U VCADDQ_ROT90_S]) (define_int_iterator VCMPEQQ [VCMPEQQ_U VCMPEQQ_S]) (define_int_iterator VCMPEQQ_N [VCMPEQQ_N_S VCMPEQQ_N_U]) (define_int_iterator VCMPNEQ_N [VCMPNEQ_N_U VCMPNEQ_N_S]) -(define_int_iterator VEORQ [VEORQ_U VEORQ_S]) (define_int_iterator VHADDQ [VHADDQ_S VHADDQ_U]) (define_int_iterator VHADDQ_N [VHADDQ_N_U VHADDQ_N_S]) (define_int_iterator VHSUBQ [VHSUBQ_S VHSUBQ_U]) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 0f04044..a5f5d75 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -1204,17 +1204,24 @@ (define_insn "mve_vcmpneq_n_" ;; ;; [veorq_u, veorq_s]) ;; -(define_insn "mve_veorq_" +(define_insn "mve_veorq_u" [ (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w")] -VEORQ)) + (xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE" - "veor %q0, %q1, %q2" + "veor\t%q0, %q1, %q2" [(set_attr "type" "mve_move") ]) +(define_expand "mve_veorq_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand") + (xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand") + (match_operand:MVE_2 2 "s_register_operand"))) + ] + "TARGET_HAVE_MVE" +) ;; ;; [vhaddq_n_u, vhaddq_n_s]) diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 669c34d..e1263b0 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -747,7 +747,7 @@ (define_insn "bic3_neon" [(set_attr "type" "neon_logic")] ) -(define_insn "xor3" +(define_insn "xor3_neon" [(set (match_operand:VDQ 0 "s_register_operand" "=w") (xor:VDQ (match_operand:VDQ 1 "s_register_operand" "w") (match_operand:VDQ 2 "s_register_operand" "w")))] diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index f111ad8..78313ea 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -608,7 +608,6 @@ (define_c_enum "unspec" [ VCMPEQQ_S VCMPEQQ_N_S VCMPNEQ_N_S - VEORQ_S VHADDQ_S VHADDQ_N_S VHSUBQ_S @@ -653,7 +652,6 @@ (define_c_enum "unspec" [ VCMPEQQ_U VCMPEQQ_N_U VCMPNEQ_N_U - VEORQ_U VHADDQ_U VHADDQ_N_U VHSUBQ_U diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index 413fb07..687134a 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -202,3 +202,18 @@ (define_expand "ior3" (match_operand:VNINOTM1 2 "neon_logic_op2" "")))] "TARGET_NEON" ) + +(define_expand "xor3" + [(set (match_operand:VNIM1 0 "s_register_operand" "") + (xor:VNIM1 (match_operand:VNIM1 1 "s_register_operand" "") + (match_operand:VNIM1 2 "s_
