[PATCH 32/55] rs6000: Add Power10 builtins
2021-06-15 Bill Schmidt
gcc/
* config/rs6000/rs6000-builtin-new.def: Add power10 and power10-64
stanzas.
---
gcc/config/rs6000/rs6000-builtin-new.def | 523 +++
1 file changed, 523 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def
b/gcc/config/rs6000/rs6000-builtin-new.def
index 8885df089a6..b0e12a0ed9b 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -2809,3 +2809,526 @@
pure vsc __builtin_vsx_xl_len_r (void *, signed long);
XL_LEN_R xl_len_r {}
+
+
+[power10]
+ const vbq __builtin_altivec_cmpge_1ti (vsq, vsq);
+CMPGE_1TI vector_nltv1ti {}
+
+ const vbq __builtin_altivec_cmpge_u1ti (vuq, vuq);
+CMPGE_U1TI vector_nltuv1ti {}
+
+ const vbq __builtin_altivec_cmple_1ti (vsq, vsq);
+CMPLE_1TI vector_ngtv1ti {}
+
+ const vbq __builtin_altivec_cmple_u1ti (vuq, vuq);
+CMPLE_U1TI vector_ngtuv1ti {}
+
+ const unsigned long long __builtin_altivec_cntmbb (vuc, const int<1>);
+VCNTMBB vec_cntmb_v16qi {}
+
+ const unsigned long long __builtin_altivec_cntmbd (vull, const int<1>);
+VCNTMBD vec_cntmb_v2di {}
+
+ const unsigned long long __builtin_altivec_cntmbh (vus, const int<1>);
+VCNTMBH vec_cntmb_v8hi {}
+
+ const unsigned long long __builtin_altivec_cntmbw (vui, const int<1>);
+VCNTMBW vec_cntmb_v4si {}
+
+ const vsq __builtin_altivec_div_v1ti (vsq, vsq);
+DIV_V1TI vsx_div_v1ti {}
+
+ const vsq __builtin_altivec_dives (vsq, vsq);
+DIVES_V1TI vsx_dives_v1ti {}
+
+ const vuq __builtin_altivec_diveu (vuq, vuq);
+DIVEU_V1TI vsx_diveu_v1ti {}
+
+ const vsq __builtin_altivec_mods (vsq, vsq);
+MODS_V1TI vsx_mods_v1ti {}
+
+ const vuq __builtin_altivec_modu (vuq, vuq);
+MODU_V1TI vsx_modu_v1ti {}
+
+ const vuc __builtin_altivec_mtvsrbm (unsigned long long);
+MTVSRBM vec_mtvsr_v16qi {}
+
+ const vull __builtin_altivec_mtvsrdm (unsigned long long);
+MTVSRDM vec_mtvsr_v2di {}
+
+ const vus __builtin_altivec_mtvsrhm (unsigned long long);
+MTVSRHM vec_mtvsr_v8hi {}
+
+ const vuq __builtin_altivec_mtvsrqm (unsigned long long);
+MTVSRQM vec_mtvsr_v1ti {}
+
+ const vui __builtin_altivec_mtvsrwm (unsigned long long);
+MTVSRWM vec_mtvsr_v4si {}
+
+ pure signed __int128 __builtin_altivec_se_lxvrbx (signed long, const signed
char *);
+SE_LXVRBX vsx_lxvrbx {lxvrse}
+
+ pure signed __int128 __builtin_altivec_se_lxvrhx (signed long, const signed
short *);
+SE_LXVRHX vsx_lxvrhx {lxvrse}
+
+ pure signed __int128 __builtin_altivec_se_lxvrwx (signed long, const signed
int *);
+SE_LXVRWX vsx_lxvrwx {lxvrse}
+
+ pure signed __int128 __builtin_altivec_se_lxvrdx (signed long, const signed
long long *);
+SE_LXVRDX vsx_lxvrdx {lxvrse}
+
+ void __builtin_altivec_tr_stxvrbx (vsq, signed long, signed char *);
+TR_STXVRBX vsx_stxvrbx {stvec}
+
+ void __builtin_altivec_tr_stxvrhx (vsq, signed long, signed int *);
+TR_STXVRHX vsx_stxvrhx {stvec}
+
+ void __builtin_altivec_tr_stxvrwx (vsq, signed long, signed short *);
+TR_STXVRWX vsx_stxvrwx {stvec}
+
+ void __builtin_altivec_tr_stxvrdx (vsq, signed long, signed long long *);
+TR_STXVRDX vsx_stxvrdx {stvec}
+
+ const vuq __builtin_altivec_udiv_v1ti (vuq, vuq);
+UDIV_V1TI vsx_udiv_v1ti {}
+
+ const vull __builtin_altivec_vcfuged (vull, vull);
+VCFUGED vcfuged {}
+
+ const vsc __builtin_altivec_vclrlb (vsc, signed int);
+VCLRLB vclrlb {}
+
+ const vsc __builtin_altivec_vclrrb (vsc, signed int);
+VCLRRB vclrrb {}
+
+ const signed int __builtin_altivec_vcmpaet_p (vsq, vsq);
+VCMPAET_P vector_ae_v1ti_p {}
+
+ const vbq __builtin_altivec_vcmpequt (vsq, vsq);
+VCMPEQUT vector_eqv1ti {}
+
+ const signed int __builtin_altivec_vcmpequt_p (signed int, vsq, vsq);
+VCMPEQUT_P vector_eq_v1ti_p {pred}
+
+ const vbq __builtin_altivec_vcmpgtst (vsq, vsq);
+VCMPGTST vector_gtv1ti {}
+
+ const signed int __builtin_altivec_vcmpgtst_p (signed int, vsq, vsq);
+VCMPGTST_P vector_gt_v1ti_p {pred}
+
+ const vbq __builtin_altivec_vcmpgtut (vuq, vuq);
+VCMPGTUT vector_gtuv1ti {}
+
+ const signed int __builtin_altivec_vcmpgtut_p (signed int, vuq, vuq);
+VCMPGTUT_P vector_gtu_v1ti_p {pred}
+
+ const vbq __builtin_altivec_vcmpnet (vsq, vsq);
+VCMPNET vcmpnet {}
+
+ const signed int __builtin_altivec_vcmpnet_p (vsq, vsq);
+VCMPNET_P vector_ne_v1ti_p {}
+
+ const vull __builtin_altivec_vclzdm (vull, vull);
+VCLZDM vclzdm {}
+
+ const vull __builtin_altivec_vctzdm (vull, vull);
+VCTZDM vctzdm {}
+
+ const vsll __builtin_altivec_vdivesd (vsll, vsll);
+VDIVESD dives_v2di {}
+
+ const vsi __builtin_altivec_vdivesw (vsi, vsi);
+VDIVESW dives_v4si {}
+
+ const vull __builtin_altivec_vdiveud (vull, vull);
+VDIVEUD diveu_v2di {}
+
+ const vui __builtin_altivec_vdiveuw (vui, vui);
+VDIVEUW diveu_v4si {}
+
+ const vsll __builtin_altivec_vdivsd (vsll, vsll);
+VDIVSD divv2di3 {}
+
+ const vsi
[PATCH 32/55] rs6000: Add Power10 builtins
2021-04-01 Bill Schmidt
gcc/
* config/rs6000/rs6000-builtin-new.def: Add power10 and power10-64
stanzas.
---
gcc/config/rs6000/rs6000-builtin-new.def | 427 +++
1 file changed, 427 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def
b/gcc/config/rs6000/rs6000-builtin-new.def
index d5dc7f24ecf..4dbd47dd470 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -2794,3 +2794,430 @@
pure vsc __builtin_vsx_xl_len_r (void *, signed long);
XL_LEN_R xl_len_r {}
+
+
+[power10]
+ const unsigned long long __builtin_altivec_cntmbb (vuc, const int<1>);
+VCNTMBB vec_cntmb_v16qi {}
+
+ const unsigned long long __builtin_altivec_cntmbd (vull, const int<1>);
+VCNTMBD vec_cntmb_v2di {}
+
+ const unsigned long long __builtin_altivec_cntmbh (vus, const int<1>);
+VCNTMBH vec_cntmb_v8hi {}
+
+ const unsigned long long __builtin_altivec_cntmbw (vui, const int<1>);
+VCNTMBW vec_cntmb_v4si {}
+
+ const vuc __builtin_altivec_mtvsrbm (unsigned long long);
+MTVSRBM vec_mtvsr_v16qi {}
+
+ const vull __builtin_altivec_mtvsrdm (unsigned long long);
+MTVSRDM vec_mtvsr_v2di {}
+
+ const vus __builtin_altivec_mtvsrhm (unsigned long long);
+MTVSRHM vec_mtvsr_v8hi {}
+
+ const vuq __builtin_altivec_mtvsrqm (unsigned long long);
+MTVSRQM vec_mtvsr_v1ti {}
+
+ const vui __builtin_altivec_mtvsrwm (unsigned long long);
+MTVSRWM vec_mtvsr_v4si {}
+
+ pure signed __int128 __builtin_altivec_se_lxvrbx (signed long, const signed
char *);
+SE_LXVRBX vsx_lxvrbx {lxvrse}
+
+ pure signed __int128 __builtin_altivec_se_lxvrhx (signed long, const signed
short *);
+SE_LXVRHX vsx_lxvrhx {lxvrse}
+
+ pure signed __int128 __builtin_altivec_se_lxvrwx (signed long, const signed
int *);
+SE_LXVRWX vsx_lxvrwx {lxvrse}
+
+ pure signed __int128 __builtin_altivec_se_lxvrdx (signed long, const signed
long long *);
+SE_LXVRDX vsx_lxvrdx {lxvrse}
+
+ void __builtin_altivec_tr_stxvrbx (vsq, signed long, signed char *);
+TR_STXVRBX vsx_stxvrbx {stvec}
+
+ void __builtin_altivec_tr_stxvrhx (vsq, signed long, signed int *);
+TR_STXVRHX vsx_stxvrhx {stvec}
+
+ void __builtin_altivec_tr_stxvrwx (vsq, signed long, signed short *);
+TR_STXVRWX vsx_stxvrwx {stvec}
+
+ void __builtin_altivec_tr_stxvrdx (vsq, signed long, signed long long *);
+TR_STXVRDX vsx_stxvrdx {stvec}
+
+ const vull __builtin_altivec_vcfuged (vull, vull);
+VCFUGED vcfuged {}
+
+ const vsc __builtin_altivec_vclrlb (vsc, signed int);
+VCLRLB vclrlb {}
+
+ const vsc __builtin_altivec_vclrrb (vsc, signed int);
+VCLRRB vclrrb {}
+
+ const vull __builtin_altivec_vclzdm (vull, vull);
+VCLZDM vclzdm {}
+
+ const vull __builtin_altivec_vctzdm (vull, vull);
+VCTZDM vctzdm {}
+
+ const vsll __builtin_altivec_vdivesd (vsll, vsll);
+VDIVESD dives_v2di {}
+
+ const vsi __builtin_altivec_vdivesw (vsi, vsi);
+VDIVESW dives_v4si {}
+
+ const vull __builtin_altivec_vdiveud (vull, vull);
+VDIVEUD diveu_v2di {}
+
+ const vui __builtin_altivec_vdiveuw (vui, vui);
+VDIVEUW diveu_v4si {}
+
+ const vsll __builtin_altivec_vdivsd (vsll, vsll);
+VDIVSD divv2di3 {}
+
+ const vsi __builtin_altivec_vdivsw (vsi, vsi);
+VDIVSW divv4si3 {}
+
+ const vull __builtin_altivec_vdivud (vull, vull);
+VDIVUD udivv2di3 {}
+
+ const vui __builtin_altivec_vdivuw (vui, vui);
+VDIVUW udivv4si3 {}
+
+ const vuc __builtin_altivec_vexpandmb (vuc);
+VEXPANDMB vec_expand_v16qi {}
+
+ const vull __builtin_altivec_vexpandmd (vull);
+VEXPANDMD vec_expand_v2di {}
+
+ const vus __builtin_altivec_vexpandmh (vus);
+VEXPANDMH vec_expand_v8hi {}
+
+ const vuq __builtin_altivec_vexpandmq (vuq);
+VEXPANDMQ vec_expand_v1ti {}
+
+ const vui __builtin_altivec_vexpandmw (vui);
+VEXPANDMW vec_expand_v4si {}
+
+ const vull __builtin_altivec_vextddvhx (vull, vull, unsigned int);
+VEXTRACTDR vextractrv2di {}
+
+ const vull __builtin_altivec_vextddvlx (vull, vull, unsigned int);
+VEXTRACTDL vextractlv2di {}
+
+ const vull __builtin_altivec_vextdubvhx (vuc, vuc, unsigned int);
+VEXTRACTBR vextractrv16qi {}
+
+ const vull __builtin_altivec_vextdubvlx (vuc, vuc, unsigned int);
+VEXTRACTBL vextractlv16qi {}
+
+ const vull __builtin_altivec_vextduhvhx (vus, vus, unsigned int);
+VEXTRACTHR vextractrv8hi {}
+
+ const vull __builtin_altivec_vextduhvlx (vus, vus, unsigned int);
+VEXTRACTHL vextractlv8hi {}
+
+ const vull __builtin_altivec_vextduwvhx (vui, vui, unsigned int);
+VEXTRACTWR vextractrv4si {}
+
+ const vull __builtin_altivec_vextduwvlx (vui, vui, unsigned int);
+VEXTRACTWL vextractlv4si {}
+
+ const signed int __builtin_altivec_vextractmb (vsc);
+VEXTRACTMB vec_extract_v16qi {}
+
+ const signed int __builtin_altivec_vextractmd (vsll);
+VEXTRACTMD vec_extract_v2di {}
+
+ const signed int __builtin_altivec_vextractmh (vss);
+
