2015-10-25 Evandro Menezes
gcc/
* config/aarch64/aarch64-cores.def: Use the Exynos M1 cost model.
* config/aarch64/aarch64.c (exynosm1_addrcost_table): New variable.
(exynosm1_regmove_cost): Likewise.
(exynosm1_vector_cost): Likewise.
(exynosm1_tunings): Likewise.
* config/arm/aarch-cost-tables.h (exynosm1_extra_costs): Likewise.
* config/arm/arm.c (arm_exynos_m1_tune): Likewise.
This patch adds the cost model for Exynos M1. This patch depends on a
couple of previous patches though,
https://gcc.gnu.org/ml/gcc-patches/2015-11/msg00505.html and
https://gcc.gnu.org/ml/gcc-patches/2015-11/msg00538.html
Please, commit if it's alright.
Thank you,
--
Evandro Menezes
>From 9b02c57fd2f2507dcc79767d7ffdb7ccec4cdd25 Mon Sep 17 00:00:00 2001
From: Evandro Menezes
Date: Thu, 5 Nov 2015 17:58:47 -0600
Subject: [PATCH] [AArch64] Add cost model for Exynos M1
2015-10-25 Evandro Menezes
gcc/
* config/aarch64/aarch64-cores.def: Use the Exynos M1 cost model.
* config/aarch64/aarch64.c (exynosm1_addrcost_table): New variable.
(exynosm1_regmove_cost): Likewise.
(exynosm1_vector_cost): Likewise.
(exynosm1_tunings): Likewise.
* config/arm/aarch-cost-tables.h (exynosm1_extra_costs): Likewise.
* config/arm/arm.c (arm_exynos_m1_tune): Likewise.
---
gcc/config/aarch64/aarch64-cores.def | 2 +-
gcc/config/aarch64/aarch64.c | 66 ++
gcc/config/arm/aarch-cost-tables.h | 103 +++
gcc/config/arm/arm-cores.def | 2 +-
gcc/config/arm/arm.c | 23
5 files changed, 194 insertions(+), 2 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def
index c17baa3..607a333 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -43,7 +43,7 @@
AARCH64_CORE("cortex-a53", cortexa53, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa53, "0x41", "0xd03")
AARCH64_CORE("cortex-a57", cortexa57, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57, "0x41", "0xd07")
AARCH64_CORE("cortex-a72", cortexa72, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa72, "0x41", "0xd08")
-AARCH64_CORE("exynos-m1", exynosm1, exynosm1, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, cortexa72, "0x53", "0x001")
+AARCH64_CORE("exynos-m1", exynosm1, exynosm1, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, exynosm1, "0x53", "0x001")
AARCH64_CORE("thunderx",thunderx, thunderx, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx, "0x43", "0x0a1")
AARCH64_CORE("xgene1", xgene1,xgene1,8A, AARCH64_FL_FOR_ARCH8, xgene1, "0x50", "0x000")
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index e7f1c07..d7d3f05 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -215,6 +215,22 @@ static const struct cpu_addrcost_table cortexa57_addrcost_table =
0, /* imm_offset */
};
+static const struct cpu_addrcost_table exynosm1_addrcost_table =
+{
+{
+ 0, /* hi */
+ 0, /* si */
+ 0, /* di */
+ 2, /* ti */
+},
+ 0, /* pre_modify */
+ 0, /* post_modify */
+ 1, /* register_offset */
+ 1, /* register_sextend */
+ 2, /* register_zextend */
+ 0, /* imm_offset */
+};
+
static const struct cpu_addrcost_table xgene1_addrcost_table =
{
{
@@ -261,6 +277,16 @@ static const struct cpu_regmove_cost cortexa53_regmove_cost =
2 /* FP2FP */
};
+static const struct cpu_regmove_cost exynosm1_regmove_cost =
+{
+ 1, /* GP2GP */
+ /* Avoid the use of slow int<->fp moves for spilling by setting
+ their cost higher than memmov_cost (actual, 4 and 9). */
+ 9, /* GP2FP */
+ 9, /* FP2GP */
+ 1 /* FP2FP */
+};
+
static const struct cpu_regmove_cost thunderx_regmove_cost =
{
2, /* GP2GP */
@@ -313,6 +339,22 @@ static const struct cpu_vector_cost cortexa57_vector_cost =
1 /* cond_not_taken_branch_cost */
};
+static const struct cpu_vector_cost exynosm1_vector_cost =
+{
+ 1, /* scalar_stmt_cost */
+ 5, /* scalar_load_cost */
+ 1, /* scalar_store_cost */
+ 3, /* vec_stmt_cost */
+ 3, /* vec_to_scalar_cost */
+ 3, /* scalar_to_vec_cost */
+ 5, /* vec_align_load_cost */
+ 5, /* vec_unalign_load_cost */
+ 1, /* vec_unalign_store_cost */
+ 1, /* vec_store_cost */
+ 1, /* cond_taken_branch_cost */
+ 1 /* cond_not_taken_branch_cost */
+};
+
/* Generic costs for vector insn classes. */
static const struct cpu_vector_cost xgene1_vector_cost =
{
@@ -436,6 +478,30 @@ static const struct tune_params cortexa72_tunings =
(AARCH64_EXTRA_TUNE_NONE) /* tune_flags. */
};
+static const struct tune_params exynosm1_tunings =
+{
+ &exynosm1_extra_costs,
+ &exynosm1_addrcost_table,
+ &exynosm1_regmove_cost,
+ &exynosm1_vector_cost,
+ &generic_branch_cost,
+ 4, /* memmov_cost */
+ 3
