Re: [PATCH 4/6] rs6000: Cleanup interleave/even_odd/vec_perm.

[Richard Henderson]

On 12/11/2011 10:44 AM, Iain Sandoe wrote:
> Note that there is no default for TARGET_BIG_ENDIAN in rs600.h - it is only 
> defined in config/rs6000/sysv4.h.

Gah.  And of course that's all I tested w/ linux.

Just change the TARGET_BIG_ENDIAN to BYTES_BIG_ENDIAN.


r~

Re: [PATCH 4/6] rs6000: Cleanup interleave/even_odd/vec_perm.

[Iain Sandoe]

On 8 Dec 2011, at 21:06, Richard Henderson wrote:


;
+
+  high = (highp == TARGET_BIG_ENDIAN ? 0 : nelt);
+


This breaks bootstrap on ppc-darwin, which came as a bit f a surprise  
to me...


... however, it would appear that TARGET_BIG_ENDIAN is not used  
anywhere else...


(plenty of {BYTES,WORDS}_BIG_ENDIAN).

Note that there is no default for TARGET_BIG_ENDIAN in rs600.h - it is  
only defined in config/rs6000/sysv4.h.


So is the patch below the correct 'obvious' fix, or was something else  
intended.

cheers
Iain

gcc:

* config/rs6000/darwin.h (TARGET_BIG_ENDIAN): Define to 1.

Index: gcc/config/rs6000/darwin.h
===
--- gcc/config/rs6000/darwin.h  (revision 182204)
+++ gcc/config/rs6000/darwin.h  (working copy)
@@ -39,6 +39,8 @@

 #define TARGET_OBJECT_FORMAT OBJECT_MACHO

+#define TARGET_BIG_ENDIAN 1
+
 /* Size of the Obj-C jump buffer.  */
 #define OBJC_JBLEN ((TARGET_64BIT) ? (26*2 + 18*2 + 129 + 1) : (26 +  
18*2 + 129 + 1))

[PATCH 4/6] rs6000: Cleanup interleave/even_odd/vec_perm.

[Richard Henderson]

Put merge-type insns in standard (vec_select (vec_concat)) form.
Delete vec_extract_{even,odd} patterns.
Delete or rename vec_interleave_{high,low} patterns.
Add vec_perm_const patterns for SPE, VSX, and Paired-Single.
---
 gcc/config/rs6000/altivec.md |  368 +++---
 gcc/config/rs6000/paired.md  |  116 ---
 gcc/config/rs6000/predicates.md  |   10 +
 gcc/config/rs6000/rs6000-builtin.def |8 +-
 gcc/config/rs6000/rs6000-modes.def   |   10 +-
 gcc/config/rs6000/rs6000-protos.h|3 +
 gcc/config/rs6000/rs6000.c   |  160 +++-
 gcc/config/rs6000/spe.md |   58 +++---
 gcc/config/rs6000/vector.md  |   74 +--
 gcc/config/rs6000/vsx.md |  151 +-
 10 files changed, 431 insertions(+), 527 deletions(-)

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 7797b65..54ca369 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -327,7 +327,7 @@
 (define_insn "*altivec_addv4sf3"
   [(set (match_operand:V4SF 0 "register_operand" "=v")
 (plus:V4SF (match_operand:V4SF 1 "register_operand" "v")
-  (match_operand:V4SF 2 "register_operand" "v")))]
+  (match_operand:V4SF 2 "register_operand" "v")))]
   "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
   "vaddfp %0,%1,%2"
   [(set_attr "type" "vecfloat")])
@@ -764,202 +764,112 @@
 
 (define_insn "altivec_vmrghb"
   [(set (match_operand:V16QI 0 "register_operand" "=v")
-(vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 
"register_operand" "v")
-  (parallel [(const_int 0)
- (const_int 8)
- (const_int 1)
- (const_int 9)
- (const_int 2)
- (const_int 10)
- (const_int 3)
- (const_int 11)
- (const_int 4)
- (const_int 12)
- (const_int 5)
- (const_int 13)
- (const_int 6)
- (const_int 14)
- (const_int 7)
- (const_int 15)]))
-(vec_select:V16QI (match_operand:V16QI 2 
"register_operand" "v")
-  (parallel [(const_int 8)
- (const_int 0)
- (const_int 9)
- (const_int 1)
- (const_int 10)
- (const_int 2)
- (const_int 11)
- (const_int 3)
- (const_int 12)
- (const_int 4)
- (const_int 13)
- (const_int 5)
- (const_int 14)
- (const_int 6)
- (const_int 15)
- (const_int 7)]))
- (const_int 21845)))]
+   (vec_select:V16QI
+ (vec_concat:V32QI
+   (match_operand:V16QI 1 "register_operand" "v")
+   (match_operand:V16QI 2 "register_operand" "v"))
+ (parallel [(const_int 0) (const_int 16)
+(const_int 1) (const_int 17)
+(const_int 2) (const_int 18)
+(const_int 3) (const_int 19)
+(const_int 4) (const_int 20)
+(const_int 5) (const_int 21)
+(const_int 6) (const_int 22)
+(const_int 7) (const_int 23)])))]
   "TARGET_ALTIVEC"
   "vmrghb %0,%1,%2"
   [(set_attr "type" "vecperm")])
 
 (define_insn "altivec_vmrghh"
   [(set (match_operand:V8HI 0 "register_operand" "=v")
-(vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 
"register_operand" "v")
-  (parallel [(const_int 0)
- (const_int 4)
- (const_int 1)
-