[PATCH V2 4/5] Implement ZKNH extensions
This patch support Zknh extension. It includes instruction's machine description, built-in funtion, and intrinsics. gcc/ChangeLog: * config/riscv/crypto.md (riscv_sha256sig0_):Add ZKNH's instructions. (riscv_sha256sig1_): Likewise. (riscv_sha256sum0_): Likewise. (riscv_sha256sum1_): Likewise. (riscv_sha512sig0h): Likewise. (riscv_sha512sig0l): Likewise. (riscv_sha512sig1h): Likewise. (riscv_sha512sig1l): Likewise. (riscv_sha512sum0r): Likewise. (riscv_sha512sum1r): Likewise. (riscv_sha512sig0): Likewise. (riscv_sha512sig1): Likewise. (riscv_sha512sum0): Likewise. (riscv_sha512sum1): Likewise. * config/riscv/riscv-builtins.cc (AVAIL): Add ZKNH's AVAIL. * config/riscv/riscv-crypto.def (RISCV_BUILTIN): Add ZKNH's built-in functions. (DIRECT_BUILTIN): Likewise. * config/riscv/riscv_scalar_crypto.h (__riscv_sha256sig0): Add ZKNH's intrinsics. (__riscv_sha256sig1): Likewise. (__riscv_sha256sum0): Likewise. (__riscv_sha256sum1): Likewise. (__riscv_sha512sig0h): Likewise. (__riscv_sha512sig0l): Likewise. (__riscv_sha512sig1h): Likewise. (__riscv_sha512sig1l): Likewise. (__riscv_sha512sum0r): Likewise. (__riscv_sha512sum1r): Likewise. (__riscv_sha512sig0): Likewise. (__riscv_sha512sig1): Likewise. (__riscv_sha512sum0): Likewise. (__riscv_sha512sum1): Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/zknh-sha256.c: New test. * gcc.target/riscv/zknh-sha512-32.c: New test. * gcc.target/riscv/zknh-sha512-64.c: New test. Co-Authored-By: SiYu Wu --- gcc/config/riscv/crypto.md| 138 ++ gcc/config/riscv/riscv-builtins.cc| 2 + gcc/config/riscv/riscv-crypto.def | 22 +++ gcc/config/riscv/riscv_scalar_crypto.h| 48 ++ gcc/testsuite/gcc.target/riscv/zknh-sha256.c | 29 .../gcc.target/riscv/zknh-sha512-32.c | 43 ++ .../gcc.target/riscv/zknh-sha512-64.c | 31 7 files changed, 313 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256.c create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md index d76a872775f..063a8025f20 100644 --- a/gcc/config/riscv/crypto.md +++ b/gcc/config/riscv/crypto.md @@ -48,6 +48,22 @@ UNSPEC_AES_ESM UNSPEC_AES_ESI UNSPEC_AES_ESMI + +;; ZKNH unspecs +UNSPEC_SHA_256_SIG0 +UNSPEC_SHA_256_SIG1 +UNSPEC_SHA_256_SUM0 +UNSPEC_SHA_256_SUM1 +UNSPEC_SHA_512_SIG0 +UNSPEC_SHA_512_SIG0H +UNSPEC_SHA_512_SIG0L +UNSPEC_SHA_512_SIG1 +UNSPEC_SHA_512_SIG1H +UNSPEC_SHA_512_SIG1L +UNSPEC_SHA_512_SUM0 +UNSPEC_SHA_512_SUM0R +UNSPEC_SHA_512_SUM1 +UNSPEC_SHA_512_SUM1R ]) ;; ZBKB extension @@ -247,3 +263,125 @@ "TARGET_ZKNE && TARGET_64BIT" "aes64esm\t%0,%1,%2" [(set_attr "type" "crypto")]) + +;; ZKNH - SHA256 + +(define_insn "riscv_sha256sig0_" + [(set (match_operand:X 0 "register_operand" "=r") +(unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_SHA_256_SIG0))] + "TARGET_ZKNH" + "sha256sig0\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha256sig1_" + [(set (match_operand:X 0 "register_operand" "=r") +(unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_SHA_256_SIG1))] + "TARGET_ZKNH" + "sha256sig1\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha256sum0_" + [(set (match_operand:X 0 "register_operand" "=r") +(unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_SHA_256_SUM0))] + "TARGET_ZKNH" + "sha256sum0\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha256sum1_" + [(set (match_operand:X 0 "register_operand" "=r") +(unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_SHA_256_SUM1))] + "TARGET_ZKNH" + "sha256sum1\t%0,%1" + [(set_attr "type" "crypto")]) + +;; ZKNH - SHA512 + +(define_insn "riscv_sha512sig0h" + [(set (match_operand:SI 0 "register_operand" "=r") +(unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_SHA_512_SIG0H))] + "TARGET_ZKNH && !TARGET_64BIT" + "sha512sig0h\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha512sig0l" + [(set (match_operand:SI 0 "register_operand" "=r") +(unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_SHA_512_SIG0L))] + "TARGET_ZKNH && !TARGET_64BIT" + "sha512sig0l\t%0,%1,%2" + [(set_attr "type"
[PATCH V2 4/5] Implement ZKNH extensions
This patch support Zknh extension. It includes instruction's machine description, built-in funtion, and intrinsics. gcc/ChangeLog: * config/riscv/crypto.md (riscv_sha256sig0_):Add ZKNH's instructions. (riscv_sha256sig1_): Likewise. (riscv_sha256sum0_): Likewise. (riscv_sha256sum1_): Likewise. (riscv_sha512sig0h): Likewise. (riscv_sha512sig0l): Likewise. (riscv_sha512sig1h): Likewise. (riscv_sha512sig1l): Likewise. (riscv_sha512sum0r): Likewise. (riscv_sha512sum1r): Likewise. (riscv_sha512sig0): Likewise. (riscv_sha512sig1): Likewise. (riscv_sha512sum0): Likewise. (riscv_sha512sum1): Likewise. * config/riscv/riscv-builtins.cc (AVAIL): Add ZKNH's AVAIL. * config/riscv/riscv-crypto.def (RISCV_BUILTIN): Add ZKNH's built-in functions. (DIRECT_BUILTIN): Likewise. * config/riscv/riscv_scalar_crypto.h (__riscv_sha256sig0): Add ZKNH's intrinsics. (__riscv_sha256sig1): Likewise. (__riscv_sha256sum0): Likewise. (__riscv_sha256sum1): Likewise. (__riscv_sha512sig0h): Likewise. (__riscv_sha512sig0l): Likewise. (__riscv_sha512sig1h): Likewise. (__riscv_sha512sig1l): Likewise. (__riscv_sha512sum0r): Likewise. (__riscv_sha512sum1r): Likewise. (__riscv_sha512sig0): Likewise. (__riscv_sha512sig1): Likewise. (__riscv_sha512sum0): Likewise. (__riscv_sha512sum1): Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/zknh-sha256.c: New test. * gcc.target/riscv/zknh-sha512-32.c: New test. * gcc.target/riscv/zknh-sha512-64.c: New test. Co-Authored-By: SiYu Wu --- gcc/config/riscv/crypto.md| 138 ++ gcc/config/riscv/riscv-builtins.cc| 2 + gcc/config/riscv/riscv-crypto.def | 22 +++ gcc/config/riscv/riscv_scalar_crypto.h| 48 ++ gcc/testsuite/gcc.target/riscv/zknh-sha256.c | 29 .../gcc.target/riscv/zknh-sha512-32.c | 43 ++ .../gcc.target/riscv/zknh-sha512-64.c | 31 7 files changed, 313 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256.c create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md index d76a872775f..063a8025f20 100644 --- a/gcc/config/riscv/crypto.md +++ b/gcc/config/riscv/crypto.md @@ -48,6 +48,22 @@ UNSPEC_AES_ESM UNSPEC_AES_ESI UNSPEC_AES_ESMI + +;; ZKNH unspecs +UNSPEC_SHA_256_SIG0 +UNSPEC_SHA_256_SIG1 +UNSPEC_SHA_256_SUM0 +UNSPEC_SHA_256_SUM1 +UNSPEC_SHA_512_SIG0 +UNSPEC_SHA_512_SIG0H +UNSPEC_SHA_512_SIG0L +UNSPEC_SHA_512_SIG1 +UNSPEC_SHA_512_SIG1H +UNSPEC_SHA_512_SIG1L +UNSPEC_SHA_512_SUM0 +UNSPEC_SHA_512_SUM0R +UNSPEC_SHA_512_SUM1 +UNSPEC_SHA_512_SUM1R ]) ;; ZBKB extension @@ -247,3 +263,125 @@ "TARGET_ZKNE && TARGET_64BIT" "aes64esm\t%0,%1,%2" [(set_attr "type" "crypto")]) + +;; ZKNH - SHA256 + +(define_insn "riscv_sha256sig0_" + [(set (match_operand:X 0 "register_operand" "=r") +(unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_SHA_256_SIG0))] + "TARGET_ZKNH" + "sha256sig0\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha256sig1_" + [(set (match_operand:X 0 "register_operand" "=r") +(unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_SHA_256_SIG1))] + "TARGET_ZKNH" + "sha256sig1\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha256sum0_" + [(set (match_operand:X 0 "register_operand" "=r") +(unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_SHA_256_SUM0))] + "TARGET_ZKNH" + "sha256sum0\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha256sum1_" + [(set (match_operand:X 0 "register_operand" "=r") +(unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_SHA_256_SUM1))] + "TARGET_ZKNH" + "sha256sum1\t%0,%1" + [(set_attr "type" "crypto")]) + +;; ZKNH - SHA512 + +(define_insn "riscv_sha512sig0h" + [(set (match_operand:SI 0 "register_operand" "=r") +(unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_SHA_512_SIG0H))] + "TARGET_ZKNH && !TARGET_64BIT" + "sha512sig0h\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha512sig0l" + [(set (match_operand:SI 0 "register_operand" "=r") +(unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_SHA_512_SIG0L))] + "TARGET_ZKNH && !TARGET_64BIT" + "sha512sig0l\t%0,%1,%2" + [(set_attr "type"
