RE: [PATCH v1] RISC-V: Add HFmode for l/ll round and rint autovec
This patch only add new modes to iterator, I failed to find a way to test it.
Maybe I can add underlying lrint autovec implment together, which is more
straightforward
to add test cases here.
Pan
From: juzhe.zh...@rivai.ai
Sent: Friday, November 10, 2023 4:16 PM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Add HFmode for l/ll round and rint autovec
No test?
juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>
From: pan2.li<mailto:pan2...@intel.com>
Date: 2023-11-10 16:14
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zh...@rivai.ai>;
pan2.li<mailto:pan2...@intel.com>;
yanzhang.wang<mailto:yanzhang.w...@intel.com>;
kito.cheng<mailto:kito.ch...@gmail.com>
Subject: [PATCH v1] RISC-V: Add HFmode for l/ll round and rint autovec
From: Pan Li mailto:pan2...@intel.com>>
The internal-fn has support the FLOATN already. This patch
would like to re-enable the vector HFmode for the autovec for
below standard name mode iterators.
1. lrint
2. llround
For now the vector HFmodes are disabled to limit the impact,
and the underlying FP16 rint/round autovec will enable this
one by one.
gcc/ChangeLog:
* config/riscv/autovec.md: Disable vector HFmode for
rint, round, ceil and floor.
* config/riscv/vector-iterators.md: Add vector HFmode
for rint, round, ceil and floor mode iterator.
Signed-off-by: Pan Li mailto:pan2...@intel.com>>
---
gcc/config/riscv/autovec.md | 26 +++-
gcc/config/riscv/vector-iterators.md | 59 +++-
2 files changed, 73 insertions(+), 12 deletions(-)
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 33722ea1139..a199caabf87 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2443,12 +2443,11 @@ (define_expand "roundeven2"
}
)
-;; Add mode_size equal check as we opened the modes for different sizes.
-;; The check will be removed soon after related codegen implemented
(define_expand "lrint2"
[(match_operand: 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_SI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+&& GET_MODE_INNER (mode) != HFmode"
{
riscv_vector::expand_vec_lrint (operands[0], operands[1], mode,
mode);
DONE;
@@ -2458,7 +2457,8 @@ (define_expand "lrint2"
(define_expand "lrint2"
[(match_operand: 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_DI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+&& GET_MODE_INNER (mode) != HFmode"
{
riscv_vector::expand_vec_lrint (operands[0], operands[1], mode,
mode);
DONE;
@@ -2468,7 +2468,8 @@ (define_expand "lrint2"
(define_expand "lround2"
[(match_operand: 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_SI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+&& GET_MODE_INNER (mode) != HFmode"
{
riscv_vector::expand_vec_lround (operands[0], operands[1], mode,
mode);
DONE;
@@ -2478,7 +2479,8 @@ (define_expand "lround2"
(define_expand "lround2"
[(match_operand: 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_DI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+&& GET_MODE_INNER (mode) != HFmode"
{
riscv_vector::expand_vec_lround (operands[0], operands[1], mode,
mode);
DONE;
@@ -2488,7 +2490,8 @@ (define_expand "lround2"
(define_expand "lceil2"
[(match_operand: 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_SI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+&& GET_MODE_INNER (mode) != HFmode"
{
riscv_vector::expand_vec_lceil (operands[0], operands[1], mode,
mode);
DONE;
@@ -2498,7 +2501,8 @@ (define_expand "lceil2"
(define_expand "lceil2"
[(match_operand: 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_DI 1 "register_operand")]
- "TARGET_VECTOR && !fl
Re: [PATCH v1] RISC-V: Add HFmode for l/ll round and rint autovec
No test?
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-11-10 16:14
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Add HFmode for l/ll round and rint autovec
From: Pan Li
The internal-fn has support the FLOATN already. This patch
would like to re-enable the vector HFmode for the autovec for
below standard name mode iterators.
1. lrint
2. llround
For now the vector HFmodes are disabled to limit the impact,
and the underlying FP16 rint/round autovec will enable this
one by one.
gcc/ChangeLog:
* config/riscv/autovec.md: Disable vector HFmode for
rint, round, ceil and floor.
* config/riscv/vector-iterators.md: Add vector HFmode
for rint, round, ceil and floor mode iterator.
Signed-off-by: Pan Li
---
gcc/config/riscv/autovec.md | 26 +++-
gcc/config/riscv/vector-iterators.md | 59 +++-
2 files changed, 73 insertions(+), 12 deletions(-)
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 33722ea1139..a199caabf87 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2443,12 +2443,11 @@ (define_expand "roundeven2"
}
)
-;; Add mode_size equal check as we opened the modes for different sizes.
-;; The check will be removed soon after related codegen implemented
(define_expand "lrint2"
[(match_operand: 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_SI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+&& GET_MODE_INNER (mode) != HFmode"
{
riscv_vector::expand_vec_lrint (operands[0], operands[1], mode,
mode);
DONE;
@@ -2458,7 +2457,8 @@ (define_expand "lrint2"
(define_expand "lrint2"
[(match_operand: 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_DI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+&& GET_MODE_INNER (mode) != HFmode"
{
riscv_vector::expand_vec_lrint (operands[0], operands[1], mode,
mode);
DONE;
@@ -2468,7 +2468,8 @@ (define_expand "lrint2"
(define_expand "lround2"
[(match_operand: 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_SI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+&& GET_MODE_INNER (mode) != HFmode"
{
riscv_vector::expand_vec_lround (operands[0], operands[1], mode,
mode);
DONE;
@@ -2478,7 +2479,8 @@ (define_expand "lround2"
(define_expand "lround2"
[(match_operand: 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_DI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+&& GET_MODE_INNER (mode) != HFmode"
{
riscv_vector::expand_vec_lround (operands[0], operands[1], mode,
mode);
DONE;
@@ -2488,7 +2490,8 @@ (define_expand "lround2"
(define_expand "lceil2"
[(match_operand: 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_SI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+&& GET_MODE_INNER (mode) != HFmode"
{
riscv_vector::expand_vec_lceil (operands[0], operands[1], mode,
mode);
DONE;
@@ -2498,7 +2501,8 @@ (define_expand "lceil2"
(define_expand "lceil2"
[(match_operand: 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_DI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+&& GET_MODE_INNER (mode) != HFmode"
{
riscv_vector::expand_vec_lceil (operands[0], operands[1], mode,
mode);
DONE;
@@ -2508,7 +2512,8 @@ (define_expand "lceil2"
(define_expand "lfloor2"
[(match_operand: 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_SI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+&& GET_MODE_INNER (mode) != HFmode"
{
riscv_vector::expa
[PATCH v1] RISC-V: Add HFmode for l/ll round and rint autovec
From: Pan Li
The internal-fn has support the FLOATN already. This patch
would like to re-enable the vector HFmode for the autovec for
below standard name mode iterators.
1. lrint
2. llround
For now the vector HFmodes are disabled to limit the impact,
and the underlying FP16 rint/round autovec will enable this
one by one.
gcc/ChangeLog:
* config/riscv/autovec.md: Disable vector HFmode for
rint, round, ceil and floor.
* config/riscv/vector-iterators.md: Add vector HFmode
for rint, round, ceil and floor mode iterator.
Signed-off-by: Pan Li
---
gcc/config/riscv/autovec.md | 26 +++-
gcc/config/riscv/vector-iterators.md | 59 +++-
2 files changed, 73 insertions(+), 12 deletions(-)
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 33722ea1139..a199caabf87 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2443,12 +2443,11 @@ (define_expand "roundeven2"
}
)
-;; Add mode_size equal check as we opened the modes for different sizes.
-;; The check will be removed soon after related codegen implemented
(define_expand "lrint2"
[(match_operand: 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_SI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+&& GET_MODE_INNER (mode) != HFmode"
{
riscv_vector::expand_vec_lrint (operands[0], operands[1], mode,
mode);
DONE;
@@ -2458,7 +2457,8 @@ (define_expand "lrint2"
(define_expand "lrint2"
[(match_operand: 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_DI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+&& GET_MODE_INNER (mode) != HFmode"
{
riscv_vector::expand_vec_lrint (operands[0], operands[1], mode,
mode);
DONE;
@@ -2468,7 +2468,8 @@ (define_expand "lrint2"
(define_expand "lround2"
[(match_operand: 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_SI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+&& GET_MODE_INNER (mode) != HFmode"
{
riscv_vector::expand_vec_lround (operands[0], operands[1], mode,
mode);
DONE;
@@ -2478,7 +2479,8 @@ (define_expand "lround2"
(define_expand "lround2"
[(match_operand: 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_DI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+&& GET_MODE_INNER (mode) != HFmode"
{
riscv_vector::expand_vec_lround (operands[0], operands[1], mode,
mode);
DONE;
@@ -2488,7 +2490,8 @@ (define_expand "lround2"
(define_expand "lceil2"
[(match_operand: 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_SI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+&& GET_MODE_INNER (mode) != HFmode"
{
riscv_vector::expand_vec_lceil (operands[0], operands[1], mode,
mode);
DONE;
@@ -2498,7 +2501,8 @@ (define_expand "lceil2"
(define_expand "lceil2"
[(match_operand: 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_DI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+&& GET_MODE_INNER (mode) != HFmode"
{
riscv_vector::expand_vec_lceil (operands[0], operands[1], mode,
mode);
DONE;
@@ -2508,7 +2512,8 @@ (define_expand "lceil2"
(define_expand "lfloor2"
[(match_operand: 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_SI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+&& GET_MODE_INNER (mode) != HFmode"
{
riscv_vector::expand_vec_lfloor (operands[0], operands[1], mode,
mode);
DONE;
@@ -2518,7 +2523,8 @@ (define_expand "lfloor2"
(define_expand "lfloor2"
[(match_operand: 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_DI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+&& GET_MODE_INNER (mode) != HFmode"
{
riscv_vector::expand_vec_lfloor (operands[0], operands[1], mode,
mode);
DONE;
diff --git a/gcc/config/riscv/vector-iterators.md
b/gcc/config/riscv/vector-iterators.md
index e80eaedc4b3..f2d9f60b631 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -3221,15 +3221,20 @@ (define_mode_attr vnnconvert [
;; V_F2SI_CONVERT: (HF, SF, DF) => SI
;; V_F2DI_CONVERT: (HF, SF, DF) => DI
;;
-;; HF requires
