RE: [PATCH v1] RISC-V: Support VLS mode for vec_set

2023-09-18 Thread Li, Pan2 via Gcc-patches 
Committed, thanks Kito.

Pan

-Original Message-
From: Kito Cheng  
Sent: Monday, September 18, 2023 11:36 AM
To: Li, Pan2 
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang 

Subject: Re: [PATCH v1] RISC-V: Support VLS mode for vec_set

LGTM

On Mon, Sep 18, 2023 at 11:27 AM Pan Li via Gcc-patches
 wrote:
>
> From: Pan Li 
>
> This patch would like to add the VLS support vec_set, both INT
> and FP are included.
>
> Give sample code as below:
>
> typedef long long vl_t \
>   __attribute__((vector_size(2 * sizeof (long long;
>
> vl_t init_vl (vl_t v, unsigned index, unsigned value)
> {
>   v[index] = value;
>
>   return v;
> }
>
> Before this patch:
> init_vl:
>   addi sp,sp,-16
>   vsetivli zero,2,e64,m1,ta,ma
>   vle64.v  v1,0(a1)
>   vse64.v  v1,0(sp)
>   slli a4,a2,32
>   srli a2,a4,29
>   add  a2,sp,a2
>   slli a3,a3,32
>   srli a3,a3,32
>   sd   a3,0(a2)
>   vle64.v  v1,0(sp)
>   vse64.v  v1,0(a0)
>   addi sp,sp,16
>   jr   ra
>
> After this patch:
> init_vl:
>   vsetivlizero,2,e64,m1,ta,ma
>   vle64.v v1,0(a1)
>   sllia3,a3,32
>   srlia3,a3,32
>   addia5,a2,1
>   vsetvli zero,a5,e64,m1,tu,ma
>   vmv.v.x v2,a3
>   vslideup.vx v1,v2,a2
>   vsetivlizero,2,e64,m1,ta,ma
>   vse64.v v1,0(a0)
>   ret
>
> Please note this patch depends the RVV SCALAR_MOVE_MERGED_OP bugfix.
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md: Extend to vls mode.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/vls/def.h: New macros.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-1.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-10.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-11.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-12.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-13.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-14.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-15.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-16.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-17.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-18.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-19.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-2.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-20.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-21.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-22.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-3.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-4.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-5.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-6.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-7.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-8.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-9.c: New test.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/config/riscv/autovec.md   |  4 +--
>  .../gcc.target/riscv/rvv/autovec/vls/def.h| 18 ++
>  .../riscv/rvv/autovec/vls/vec-set-1.c | 35 +++
>  .../riscv/rvv/autovec/vls/vec-set-10.c| 31 
>  .../riscv/rvv/autovec/vls/vec-set-11.c| 29 +++
>  .../riscv/rvv/autovec/vls/vec-set-12.c| 21 +++
>  .../riscv/rvv/autovec/vls/vec-set-13.c| 20 +++
>  .../riscv/rvv/autovec/vls/vec-set-14.c| 19 ++
>  .../riscv/rvv/autovec/vls/vec-set-15.c| 18 ++
>  .../riscv/rvv/autovec/vls/vec-set-16.c| 21 +++
>  .../riscv/rvv/autovec/vls/vec-set-17.c| 20 +++
>  .../riscv/rvv/autovec/vls/vec-set-18.c| 19 ++
>  .../riscv/rvv/autovec/vls/vec-set-19.c| 18 ++
>  .../riscv/rvv/autovec/vls/vec-set-2.c | 33 +
>  .../riscv/rvv/autovec/vls/vec-set-20.c| 20 +++
>  .../riscv/rvv/autovec/vls/vec-set-21.c| 19 ++
>  .../riscv/rvv/autovec/vls/vec-set-22.c| 18 ++
>  .../riscv/rvv/autovec/vls/vec-set-3.c | 31 
>  .../riscv/rvv/autovec/vls/vec-set-4.c | 29 +++
>  .../riscv/rvv/autovec/vls/vec-set-5.c | 35 +++
>  .../riscv/rvv/autovec/vls/vec-set-6.c | 33 +
>  .../riscv/rvv/autovec/vls/vec-set-7.c | 31 
>  .../riscv/rvv/autovec/vls/vec-set-8.c | 29 +++
>

Re: [PATCH v1] RISC-V: Support VLS mode for vec_set

2023-09-17 Thread Kito Cheng via Gcc-patches 
LGTM

On Mon, Sep 18, 2023 at 11:27 AM Pan Li via Gcc-patches
 wrote:
>
> From: Pan Li 
>
> This patch would like to add the VLS support vec_set, both INT
> and FP are included.
>
> Give sample code as below:
>
> typedef long long vl_t \
>   __attribute__((vector_size(2 * sizeof (long long;
>
> vl_t init_vl (vl_t v, unsigned index, unsigned value)
> {
>   v[index] = value;
>
>   return v;
> }
>
> Before this patch:
> init_vl:
>   addi sp,sp,-16
>   vsetivli zero,2,e64,m1,ta,ma
>   vle64.v  v1,0(a1)
>   vse64.v  v1,0(sp)
>   slli a4,a2,32
>   srli a2,a4,29
>   add  a2,sp,a2
>   slli a3,a3,32
>   srli a3,a3,32
>   sd   a3,0(a2)
>   vle64.v  v1,0(sp)
>   vse64.v  v1,0(a0)
>   addi sp,sp,16
>   jr   ra
>
> After this patch:
> init_vl:
>   vsetivlizero,2,e64,m1,ta,ma
>   vle64.v v1,0(a1)
>   sllia3,a3,32
>   srlia3,a3,32
>   addia5,a2,1
>   vsetvli zero,a5,e64,m1,tu,ma
>   vmv.v.x v2,a3
>   vslideup.vx v1,v2,a2
>   vsetivlizero,2,e64,m1,ta,ma
>   vse64.v v1,0(a0)
>   ret
>
> Please note this patch depends the RVV SCALAR_MOVE_MERGED_OP bugfix.
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md: Extend to vls mode.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/vls/def.h: New macros.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-1.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-10.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-11.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-12.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-13.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-14.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-15.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-16.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-17.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-18.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-19.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-2.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-20.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-21.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-22.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-3.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-4.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-5.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-6.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-7.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-8.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-9.c: New test.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/config/riscv/autovec.md   |  4 +--
>  .../gcc.target/riscv/rvv/autovec/vls/def.h| 18 ++
>  .../riscv/rvv/autovec/vls/vec-set-1.c | 35 +++
>  .../riscv/rvv/autovec/vls/vec-set-10.c| 31 
>  .../riscv/rvv/autovec/vls/vec-set-11.c| 29 +++
>  .../riscv/rvv/autovec/vls/vec-set-12.c| 21 +++
>  .../riscv/rvv/autovec/vls/vec-set-13.c| 20 +++
>  .../riscv/rvv/autovec/vls/vec-set-14.c| 19 ++
>  .../riscv/rvv/autovec/vls/vec-set-15.c| 18 ++
>  .../riscv/rvv/autovec/vls/vec-set-16.c| 21 +++
>  .../riscv/rvv/autovec/vls/vec-set-17.c| 20 +++
>  .../riscv/rvv/autovec/vls/vec-set-18.c| 19 ++
>  .../riscv/rvv/autovec/vls/vec-set-19.c| 18 ++
>  .../riscv/rvv/autovec/vls/vec-set-2.c | 33 +
>  .../riscv/rvv/autovec/vls/vec-set-20.c| 20 +++
>  .../riscv/rvv/autovec/vls/vec-set-21.c| 19 ++
>  .../riscv/rvv/autovec/vls/vec-set-22.c| 18 ++
>  .../riscv/rvv/autovec/vls/vec-set-3.c | 31 
>  .../riscv/rvv/autovec/vls/vec-set-4.c | 29 +++
>  .../riscv/rvv/autovec/vls/vec-set-5.c | 35 +++
>  .../riscv/rvv/autovec/vls/vec-set-6.c | 33 +
>  .../riscv/rvv/autovec/vls/vec-set-7.c | 31 
>  .../riscv/rvv/autovec/vls/vec-set-8.c | 29 +++
>  .../riscv/rvv/autovec/vls/vec-set-9.c | 33 +
>  24 files changed, 582 insertions(+), 2 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-1.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-10.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-11.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-12.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-13.c
>  create mode 100644 
>

[PATCH v1] RISC-V: Support VLS mode for vec_set

2023-09-17 Thread Pan Li via Gcc-patches 
From: Pan Li 

This patch would like to add the VLS support vec_set, both INT
and FP are included.

Give sample code as below:

typedef long long vl_t \
  __attribute__((vector_size(2 * sizeof (long long;

vl_t init_vl (vl_t v, unsigned index, unsigned value)
{
  v[index] = value;

  return v;
}

Before this patch:
init_vl:
  addi sp,sp,-16
  vsetivli zero,2,e64,m1,ta,ma
  vle64.v  v1,0(a1)
  vse64.v  v1,0(sp)
  slli a4,a2,32
  srli a2,a4,29
  add  a2,sp,a2
  slli a3,a3,32
  srli a3,a3,32
  sd   a3,0(a2)
  vle64.v  v1,0(sp)
  vse64.v  v1,0(a0)
  addi sp,sp,16
  jr   ra

After this patch:
init_vl:
  vsetivlizero,2,e64,m1,ta,ma
  vle64.v v1,0(a1)
  sllia3,a3,32
  srlia3,a3,32
  addia5,a2,1
  vsetvli zero,a5,e64,m1,tu,ma
  vmv.v.x v2,a3
  vslideup.vx v1,v2,a2
  vsetivlizero,2,e64,m1,ta,ma
  vse64.v v1,0(a0)
  ret

Please note this patch depends the RVV SCALAR_MOVE_MERGED_OP bugfix.

gcc/ChangeLog:

* config/riscv/autovec.md: Extend to vls mode.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vls/def.h: New macros.
* gcc.target/riscv/rvv/autovec/vls/vec-set-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-10.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-11.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-12.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-13.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-14.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-15.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-16.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-17.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-18.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-19.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-20.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-21.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-22.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-5.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-6.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-7.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-8.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-9.c: New test.

Signed-off-by: Pan Li 
---
 gcc/config/riscv/autovec.md   |  4 +--
 .../gcc.target/riscv/rvv/autovec/vls/def.h| 18 ++
 .../riscv/rvv/autovec/vls/vec-set-1.c | 35 +++
 .../riscv/rvv/autovec/vls/vec-set-10.c| 31 
 .../riscv/rvv/autovec/vls/vec-set-11.c| 29 +++
 .../riscv/rvv/autovec/vls/vec-set-12.c| 21 +++
 .../riscv/rvv/autovec/vls/vec-set-13.c| 20 +++
 .../riscv/rvv/autovec/vls/vec-set-14.c| 19 ++
 .../riscv/rvv/autovec/vls/vec-set-15.c| 18 ++
 .../riscv/rvv/autovec/vls/vec-set-16.c| 21 +++
 .../riscv/rvv/autovec/vls/vec-set-17.c| 20 +++
 .../riscv/rvv/autovec/vls/vec-set-18.c| 19 ++
 .../riscv/rvv/autovec/vls/vec-set-19.c| 18 ++
 .../riscv/rvv/autovec/vls/vec-set-2.c | 33 +
 .../riscv/rvv/autovec/vls/vec-set-20.c| 20 +++
 .../riscv/rvv/autovec/vls/vec-set-21.c| 19 ++
 .../riscv/rvv/autovec/vls/vec-set-22.c| 18 ++
 .../riscv/rvv/autovec/vls/vec-set-3.c | 31 
 .../riscv/rvv/autovec/vls/vec-set-4.c | 29 +++
 .../riscv/rvv/autovec/vls/vec-set-5.c | 35 +++
 .../riscv/rvv/autovec/vls/vec-set-6.c | 33 +
 .../riscv/rvv/autovec/vls/vec-set-7.c | 31 
 .../riscv/rvv/autovec/vls/vec-set-8.c | 29 +++
 .../riscv/rvv/autovec/vls/vec-set-9.c | 33 +
 24 files changed, 582 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-11.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-12.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-13.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-14.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-15.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-17.c
 create