RE: [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3

2024-06-13 Thread Li, Pan2 
Thanks Juzhe, will commit the series after the middle-end patch.

Pan

From: juzhe.zh...@rivai.ai 
Sent: Friday, June 14, 2024 10:24 AM
To: Li, Pan2 ; gcc-patches 
Cc: kito.cheng ; jeffreyalaw ; 
Robin Dapp ; Li, Pan2 
Subject: Re: [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB 
form 3

LGTM


juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>

From: pan2.li<mailto:pan2...@intel.com>
Date: 2024-06-14 10:13
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zh...@rivai.ai>; 
kito.cheng<mailto:kito.ch...@gmail.com>; 
jeffreyalaw<mailto:jeffreya...@gmail.com>; 
rdapp.gcc<mailto:rdapp@gmail.com>; Pan Li<mailto:pan2...@intel.com>
Subject: [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3
From: Pan Li mailto:pan2...@intel.com>>

After the middle-end support the form 3 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 3 of unsigned .SAT_SUB.

Form 3:
  #define SAT_SUB_U_3(T) \
  T sat_sub_u_3_##T (T x, T y) \
  { \
return x > y ? x - y : 0; \
  }

Passed the rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-10.c: New test.
* gcc.target/riscv/sat_u_sub-11.c: New test.
* gcc.target/riscv/sat_u_sub-12.c: New test.
* gcc.target/riscv/sat_u_sub-9.c: New test.
* gcc.target/riscv/sat_u_sub-run-10.c: New test.
* gcc.target/riscv/sat_u_sub-run-11.c: New test.
* gcc.target/riscv/sat_u_sub-run-12.c: New test.
* gcc.target/riscv/sat_u_sub-run-9.c: New test.

Signed-off-by: Pan Li mailto:pan2...@intel.com>>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h|  8 ++
gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c | 19 ++
gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c | 18 +
gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c | 17 +
gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c  | 18 +
.../gcc.target/riscv/sat_u_sub-run-10.c   | 25 +++
.../gcc.target/riscv/sat_u_sub-run-11.c   | 25 +++
.../gcc.target/riscv/sat_u_sub-run-12.c   | 25 +++
.../gcc.target/riscv/sat_u_sub-run-9.c| 25 +++
9 files changed, 180 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-9.c

diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h 
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index bc9a372b6df..50c65cdea49 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -92,8 +92,16 @@ sat_u_sub_##T##_fmt_2 (T x, T y)  \
   return (x - y) & (-(T)(x > y)); \
}
+#define DEF_SAT_U_SUB_FMT_3(T)\
+T __attribute__((noinline))   \
+sat_u_sub_##T##_fmt_3 (T x, T y)  \
+{ \
+  return x > y ? x - y : 0;   \
+}
+
#define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
#define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
+#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
#define DEF_VEC_SAT_U_SUB_FMT_1(T)   \
void __attribute__((noinline))   \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c
new file mode 100644
index 000..6e78164865f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_3:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_3(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c
new file mode 100644
index 000..84e34657f55
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -

Re: [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3

2024-06-13 Thread juzhe.zh...@rivai.ai 
LGTM



juzhe.zh...@rivai.ai
 
From: pan2.li
Date: 2024-06-14 10:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3
From: Pan Li 
 
After the middle-end support the form 3 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 3 of unsigned .SAT_SUB.
 
Form 3:
  #define SAT_SUB_U_3(T) \
  T sat_sub_u_3_##T (T x, T y) \
  { \
return x > y ? x - y : 0; \
  }
 
Passed the rv64gcv fully regression test.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-10.c: New test.
* gcc.target/riscv/sat_u_sub-11.c: New test.
* gcc.target/riscv/sat_u_sub-12.c: New test.
* gcc.target/riscv/sat_u_sub-9.c: New test.
* gcc.target/riscv/sat_u_sub-run-10.c: New test.
* gcc.target/riscv/sat_u_sub-run-11.c: New test.
* gcc.target/riscv/sat_u_sub-run-12.c: New test.
* gcc.target/riscv/sat_u_sub-run-9.c: New test.
 
Signed-off-by: Pan Li 
---
gcc/testsuite/gcc.target/riscv/sat_arith.h|  8 ++
gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c | 19 ++
gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c | 18 +
gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c | 17 +
gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c  | 18 +
.../gcc.target/riscv/sat_u_sub-run-10.c   | 25 +++
.../gcc.target/riscv/sat_u_sub-run-11.c   | 25 +++
.../gcc.target/riscv/sat_u_sub-run-12.c   | 25 +++
.../gcc.target/riscv/sat_u_sub-run-9.c| 25 +++
9 files changed, 180 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-9.c
 
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h 
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index bc9a372b6df..50c65cdea49 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -92,8 +92,16 @@ sat_u_sub_##T##_fmt_2 (T x, T y)  \
   return (x - y) & (-(T)(x > y)); \
}
+#define DEF_SAT_U_SUB_FMT_3(T)\
+T __attribute__((noinline))   \
+sat_u_sub_##T##_fmt_3 (T x, T y)  \
+{ \
+  return x > y ? x - y : 0;   \
+}
+
#define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
#define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
+#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
#define DEF_VEC_SAT_U_SUB_FMT_1(T)   \
void __attribute__((noinline))   \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c
new file mode 100644
index 000..6e78164865f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_3:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_3(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c
new file mode 100644
index 000..84e34657f55
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint32_t_fmt_3:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_SUB_FMT_3(uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c
new file mode 100644
index

[PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3

2024-06-13 Thread pan2 . li 
From: Pan Li 

After the middle-end support the form 3 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 3 of unsigned .SAT_SUB.

Form 3:
  #define SAT_SUB_U_3(T) \
  T sat_sub_u_3_##T (T x, T y) \
  { \
return x > y ? x - y : 0; \
  }

Passed the rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-10.c: New test.
* gcc.target/riscv/sat_u_sub-11.c: New test.
* gcc.target/riscv/sat_u_sub-12.c: New test.
* gcc.target/riscv/sat_u_sub-9.c: New test.
* gcc.target/riscv/sat_u_sub-run-10.c: New test.
* gcc.target/riscv/sat_u_sub-run-11.c: New test.
* gcc.target/riscv/sat_u_sub-run-12.c: New test.
* gcc.target/riscv/sat_u_sub-run-9.c: New test.

Signed-off-by: Pan Li 
---
 gcc/testsuite/gcc.target/riscv/sat_arith.h|  8 ++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c | 19 ++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c | 18 +
 gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c | 17 +
 gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c  | 18 +
 .../gcc.target/riscv/sat_u_sub-run-10.c   | 25 +++
 .../gcc.target/riscv/sat_u_sub-run-11.c   | 25 +++
 .../gcc.target/riscv/sat_u_sub-run-12.c   | 25 +++
 .../gcc.target/riscv/sat_u_sub-run-9.c| 25 +++
 9 files changed, 180 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-11.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-12.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-9.c

diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h 
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index bc9a372b6df..50c65cdea49 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -92,8 +92,16 @@ sat_u_sub_##T##_fmt_2 (T x, T y)  \
   return (x - y) & (-(T)(x > y)); \
 }
 
+#define DEF_SAT_U_SUB_FMT_3(T)\
+T __attribute__((noinline))   \
+sat_u_sub_##T##_fmt_3 (T x, T y)  \
+{ \
+  return x > y ? x - y : 0;   \
+}
+
 #define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
 #define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
+#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
 
 #define DEF_VEC_SAT_U_SUB_FMT_1(T)   \
 void __attribute__((noinline))   \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c
new file mode 100644
index 000..6e78164865f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_3:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_3(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c
new file mode 100644
index 000..84e34657f55
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint32_t_fmt_3:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_SUB_FMT_3(uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c
new file mode 100644
index 000..eea282b21ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-