Re: [PATCH v1 3/7] RISC-V: Add testcases for unsigned .SAT_ADD vector form 4

2024-06-18 Thread ?????? 
lgtm








 --Reply to Message--
 On Mon, Jun 17, 2024 22:34 PM pan2.li

[PATCH v1 3/7] RISC-V: Add testcases for unsigned .SAT_ADD vector form 4

2024-06-17 Thread pan2 . li 
From: Pan Li 

After the middle-end support the form 4 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 4.

Form 4:
  #define DEF_VEC_SAT_U_ADD_FMT_4(T)   \
  void __attribute__((noinline))   \
  vec_sat_u_add_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \
  {\
unsigned i;\
for (i = 0; i < limit; i++)\
  {\
T x = op_1[i]; \
T y = op_2[i]; \
T ret; \
out[i] = __builtin_add_overflow (x, y, &ret) ? -1 : ret;   \
  }\
  }

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-13.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-14.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-15.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-16.c: New test.

Passed the rv64gcv regression tests.

Signed-off-by: Pan Li 
---
 .../riscv/rvv/autovec/binop/vec_sat_arith.h   | 17 +
 .../rvv/autovec/binop/vec_sat_u_add-13.c  | 19 +
 .../rvv/autovec/binop/vec_sat_u_add-14.c  | 20 +
 .../rvv/autovec/binop/vec_sat_u_add-15.c  | 20 +
 .../rvv/autovec/binop/vec_sat_u_add-16.c  | 20 +
 .../rvv/autovec/binop/vec_sat_u_add-run-13.c  | 75 +++
 .../rvv/autovec/binop/vec_sat_u_add-run-14.c  | 75 +++
 .../rvv/autovec/binop/vec_sat_u_add-run-15.c  | 75 +++
 .../rvv/autovec/binop/vec_sat_u_add-run-16.c  | 75 +++
 9 files changed, 396 insertions(+)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-13.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-14.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-15.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-16.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index 76f393fffbd..e00769e35b6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -47,6 +47,20 @@ vec_sat_u_add_##T##_fmt_3 (T *out, T *op_1, T *op_2, 
unsigned limit) \
 }\
 }
 
+#define DEF_VEC_SAT_U_ADD_FMT_4(T)   \
+void __attribute__((noinline))   \
+vec_sat_u_add_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \
+{\
+  unsigned i;\
+  for (i = 0; i < limit; i++)\
+{\
+  T x = op_1[i]; \
+  T y = op_2[i]; \
+  T ret; \
+  out[i] = __builtin_add_overflow (x, y, &ret) ? -1 : ret;   \
+}\
+}
+
 #define RUN_VEC_SAT_U_ADD_FMT_1(T, out, op_1, op_2, N) \
   vec_sat_u_add_##T##_fmt_1(out, op_1, op_2, N)
 
@@ -56,6 +70,9 @@ vec_sat_u_add_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned 
limit) \
 #define RUN_VEC_SAT_U_ADD_FMT_3(T, out, op_1, op_2, N) \
   vec_sat_u_add_##T##_fmt_3(out, op_1, op_2, N)
 
+#define RUN_VEC_SAT_U_ADD_FMT_4(T, out, op_1, op_2, N) \
+  vec_sat_u_add_##T##_fmt_4(out, op_1, op_2, N)
+