From: Pan Li
After the middle-end support the form 6 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 6.
Form 6:
#define DEF_VEC_SAT_U_ADD_FMT_6(T) \
void __attribute__((noinline)) \
vec_sat_u_add_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \
{\
unsigned i;\
for (i = 0; i < limit; i++)\
{\
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = x <= (T)(x + y) ? (x + y) : -1; \
}\
}
Passed the rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-21.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-22.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-23.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-24.c: New test.
Signed-off-by: Pan Li
---
.../riscv/rvv/autovec/binop/vec_sat_arith.h | 16
.../rvv/autovec/binop/vec_sat_u_add-21.c | 19 +
.../rvv/autovec/binop/vec_sat_u_add-22.c | 20 +
.../rvv/autovec/binop/vec_sat_u_add-23.c | 20 +
.../rvv/autovec/binop/vec_sat_u_add-24.c | 20 +
.../rvv/autovec/binop/vec_sat_u_add-run-21.c | 75 +++
.../rvv/autovec/binop/vec_sat_u_add-run-22.c | 75 +++
.../rvv/autovec/binop/vec_sat_u_add-run-23.c | 75 +++
.../rvv/autovec/binop/vec_sat_u_add-run-24.c | 75 +++
9 files changed, 395 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-21.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-22.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-23.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-24.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index 1f2ee31577d..0f08822cbeb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -75,6 +75,19 @@ vec_sat_u_add_##T##_fmt_5 (T *out, T *op_1, T *op_2,
unsigned limit) \
}\
}
+#define DEF_VEC_SAT_U_ADD_FMT_6(T) \
+void __attribute__((noinline)) \
+vec_sat_u_add_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \
+{\
+ unsigned i;\
+ for (i = 0; i < limit; i++)\
+{\
+ T x = op_1[i]; \
+ T y = op_2[i]; \
+ out[i] = x <= (T)(x + y) ? (x + y) : -1; \
+}\
+}
+
#define RUN_VEC_SAT_U_ADD_FMT_1(T, out, op_1, op_2, N) \
vec_sat_u_add_##T##_fmt_1(out, op_1, op_2, N)
@@ -90,6 +103,9 @@ vec_sat_u_add_##T##_fmt_5 (T *out, T *op_1, T *op_2,
unsigned limit) \
#define RUN_VEC_SAT_U_ADD_FMT_5(T, out, op_1, op_2, N) \
vec_sat_u_add_##T##_fmt_5(out, op_1, op_2, N)
+#define RUN_VEC_SAT_U_ADD_FMT_6(T, out, op_1, op_2, N) \
+ vec_sat_u_add_##T##_fmt_6(out, op_1, op_2, N)
+
/**/
/* Saturation Sub (Unsigned and Signed)
