Re: Re: [PATCH v2] RISC-V: Bugfix for RTL check[PR111533]
Committed, thanks juzhe. -- Li Xu >LGTM. Thanks for fixing it. > > > >juzhe.zh...@rivai.ai > >From: Li Xu >Date: 2023-09-28 09:33 >To: gcc-patches >CC: kito.cheng; palmer; juzhe.zhong; xuli >Subject: [PATCH v2] RISC-V: Bugfix for RTL check[PR111533] >From: xuli > >Consider the flowing situation: >BB5: local_dem(RVV Insn 1, AVL(reg zero)) >RVV Insn 1: vmv.s.x, AVL (const_int 1) >RVV Insn 2: vredsum.vs, AVL(reg zero) > >vmv.s.x has vl operand, the following code will get >avl (cosnt_int) from RVV Insn 1. >rtx avl = has_vl_op (insn->rtl ()) ? get_vl (insn->rtl ()) > : dem.get_avl (); > >If use REGNO for const_int, the compiler will crash: > >during RTL pass: vsetvl >res_debug.c: In function '__dn_count_labels': >res_debug.c:1050:1: internal compiler error: RTL check: expected code 'reg', >have 'const_int' in rhs_regno, at rtl.h:1934 >1050 | } > | ^ >0x8fb169 rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, int, >char const*) >../.././gcc/gcc/rtl.cc:770 >0x1399818 rhs_regno(rtx_def const*) >../.././gcc/gcc/rtl.h:1934 >0x1399818 anticipatable_occurrence_p >../.././gcc/gcc/config/riscv/riscv-vsetvl.cc:348 > >So in this case avl should be obtained from dem. > >Another issue is caused by the following code: >HOST_WIDE_INT diff = INTVAL (builder.elt (i)) - i; > >during RTL pass: expand >../../.././gcc/libgfortran/generated/matmul_c4.c: In function 'matmul_c4': >../../.././gcc/libgfortran/generated/matmul_c4.c:2906:39: internal compiler >error: RTL check: >expected code 'const_int', have 'const_poly_int' in expand_const_vector, >at config/riscv/riscv-v.cc:1149 > >The builder.elt (i) can be either const_int or const_poly_int. > >PR target/111533 > >gcc/ChangeLog: > >* config/riscv/riscv-v.cc (expand_const_vector): Fix bug. >* config/riscv/riscv-vsetvl.cc (anticipatable_occurrence_p): Fix bug. > >gcc/testsuite/ChangeLog: > >* gcc.target/riscv/rvv/base/pr111533-1.c: New test. >* gcc.target/riscv/rvv/base/pr111533-2.c: New test. >--- >gcc/config/riscv/riscv-v.cc | 5 ++-- >gcc/config/riscv/riscv-vsetvl.cc | 3 +- >.../gcc.target/riscv/rvv/base/pr111533-1.c | 15 ++ >.../gcc.target/riscv/rvv/base/pr111533-2.c | 29 +++ >4 files changed, 48 insertions(+), 4 deletions(-) >create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-1.c >create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-2.c > >diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc >index 359fb2ced8b..26700cfc732 100644 >--- a/gcc/config/riscv/riscv-v.cc >+++ b/gcc/config/riscv/riscv-v.cc >@@ -1149,8 +1149,9 @@ expand_const_vector (rtx target, rtx src) > for (unsigned int i = 0; i < v.npatterns (); ++i) >{ > /* Calculate the diff between the target sequence and >- vid sequence. */ >- HOST_WIDE_INT diff = INTVAL (builder.elt (i)) - i; >+ vid sequence. The elt (i) can be either const_int or >+ const_poly_int. */ >+ poly_int64 diff = rtx_to_poly_int64 (builder.elt (i)) - i; > v.quick_push (gen_int_mode (diff, v.inner_mode ())); >} > /* Step 2: Generate result = VID + diff. */ >diff --git a/gcc/config/riscv/riscv-vsetvl.cc >b/gcc/config/riscv/riscv-vsetvl.cc >index 7af33e7ea6f..af8c31d873c 100644 >--- a/gcc/config/riscv/riscv-vsetvl.cc >+++ b/gcc/config/riscv/riscv-vsetvl.cc >@@ -307,8 +307,7 @@ anticipatable_occurrence_p (const bb_info *bb, const >vector_insn_info dem) > if (dem.has_avl_reg ()) > { > /* rs1 (avl) are not modified in the basic block prior to the VSETVL. >*/ >- rtx avl >- = has_vl_op (insn->rtl ()) ? get_vl (insn->rtl ()) : dem.get_avl (); >+ rtx avl = dem.get_avl_or_vl_reg (); > if (dem.dirty_p ()) >{ > gcc_assert (!vsetvl_insn_p (insn->rtl ())); >diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-1.c >b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-1.c >new file mode 100644 >index 000..aba26dfac89 >--- /dev/null >+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-1.c >@@ -0,0 +1,15 @@ >+/* { dg-do compile } */ >+/* { dg-options "-march=rv64gcv -mabi=lp64d -O2 -ffast-math -ftree-vectorize" >} */ >+ >+#include >+ >+typedef _Complex float GFC_COMPLEX_4; >+ >+void >+test (GFC_COMPLEX_4 *a, GFC_COMPLEX_4 *b, GFC_COMPLEX_4 c, ptrdiff_t i, >ptrdiff_t j) >+{ >+ ptrdiff_t l; >+ for (l = 0; l <= i; ++l) >+ c += b[l] * a[j]; >+ b[j] = c; >+} >diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-2.c >b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-2.c &
Re: [PATCH v2] RISC-V: Bugfix for RTL check[PR111533]
LGTM. Thanks for fixing it. juzhe.zh...@rivai.ai From: Li Xu Date: 2023-09-28 09:33 To: gcc-patches CC: kito.cheng; palmer; juzhe.zhong; xuli Subject: [PATCH v2] RISC-V: Bugfix for RTL check[PR111533] From: xuli Consider the flowing situation: BB5: local_dem(RVV Insn 1, AVL(reg zero)) RVV Insn 1: vmv.s.x, AVL (const_int 1) RVV Insn 2: vredsum.vs, AVL(reg zero) vmv.s.x has vl operand, the following code will get avl (cosnt_int) from RVV Insn 1. rtx avl = has_vl_op (insn->rtl ()) ? get_vl (insn->rtl ()) : dem.get_avl (); If use REGNO for const_int, the compiler will crash: during RTL pass: vsetvl res_debug.c: In function '__dn_count_labels': res_debug.c:1050:1: internal compiler error: RTL check: expected code 'reg', have 'const_int' in rhs_regno, at rtl.h:1934 1050 | } | ^ 0x8fb169 rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, int, char const*) ../.././gcc/gcc/rtl.cc:770 0x1399818 rhs_regno(rtx_def const*) ../.././gcc/gcc/rtl.h:1934 0x1399818 anticipatable_occurrence_p ../.././gcc/gcc/config/riscv/riscv-vsetvl.cc:348 So in this case avl should be obtained from dem. Another issue is caused by the following code: HOST_WIDE_INT diff = INTVAL (builder.elt (i)) - i; during RTL pass: expand ../../.././gcc/libgfortran/generated/matmul_c4.c: In function 'matmul_c4': ../../.././gcc/libgfortran/generated/matmul_c4.c:2906:39: internal compiler error: RTL check: expected code 'const_int', have 'const_poly_int' in expand_const_vector, at config/riscv/riscv-v.cc:1149 The builder.elt (i) can be either const_int or const_poly_int. PR target/111533 gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_const_vector): Fix bug. * config/riscv/riscv-vsetvl.cc (anticipatable_occurrence_p): Fix bug. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr111533-1.c: New test. * gcc.target/riscv/rvv/base/pr111533-2.c: New test. --- gcc/config/riscv/riscv-v.cc | 5 ++-- gcc/config/riscv/riscv-vsetvl.cc | 3 +- .../gcc.target/riscv/rvv/base/pr111533-1.c| 15 ++ .../gcc.target/riscv/rvv/base/pr111533-2.c| 29 +++ 4 files changed, 48 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-2.c diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 359fb2ced8b..26700cfc732 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1149,8 +1149,9 @@ expand_const_vector (rtx target, rtx src) for (unsigned int i = 0; i < v.npatterns (); ++i) { /* Calculate the diff between the target sequence and - vid sequence. */ - HOST_WIDE_INT diff = INTVAL (builder.elt (i)) - i; + vid sequence. The elt (i) can be either const_int or + const_poly_int. */ + poly_int64 diff = rtx_to_poly_int64 (builder.elt (i)) - i; v.quick_push (gen_int_mode (diff, v.inner_mode ())); } /* Step 2: Generate result = VID + diff. */ diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index 7af33e7ea6f..af8c31d873c 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -307,8 +307,7 @@ anticipatable_occurrence_p (const bb_info *bb, const vector_insn_info dem) if (dem.has_avl_reg ()) { /* rs1 (avl) are not modified in the basic block prior to the VSETVL. */ - rtx avl - = has_vl_op (insn->rtl ()) ? get_vl (insn->rtl ()) : dem.get_avl (); + rtx avl = dem.get_avl_or_vl_reg (); if (dem.dirty_p ()) { gcc_assert (!vsetvl_insn_p (insn->rtl ())); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-1.c new file mode 100644 index 000..aba26dfac89 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O2 -ffast-math -ftree-vectorize" } */ + +#include + +typedef _Complex float GFC_COMPLEX_4; + +void +test (GFC_COMPLEX_4 *a, GFC_COMPLEX_4 *b, GFC_COMPLEX_4 c, ptrdiff_t i, ptrdiff_t j) +{ + ptrdiff_t l; + for (l = 0; l <= i; ++l) +c += b[l] * a[j]; + b[j] = c; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-2.c new file mode 100644 index 000..a4d2011b74b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-2.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */ + +#include + +/* Return the number of DNS hierarchy levels in the name. */ +int +test (const char *name) { + int i, len, count; + + len = strlen(name); + for (i = 0, count = 0; i < len; i++) { + /* XXX need to check for \. or use named's nlabels(). */ + if (name[i] == '.') + count++; + } + + /* don't count initial wildcard *
[PATCH v2] RISC-V: Bugfix for RTL check[PR111533]
From: xuli Consider the flowing situation: BB5: local_dem(RVV Insn 1, AVL(reg zero)) RVV Insn 1: vmv.s.x, AVL (const_int 1) RVV Insn 2: vredsum.vs, AVL(reg zero) vmv.s.x has vl operand, the following code will get avl (cosnt_int) from RVV Insn 1. rtx avl = has_vl_op (insn->rtl ()) ? get_vl (insn->rtl ()) : dem.get_avl (); If use REGNO for const_int, the compiler will crash: during RTL pass: vsetvl res_debug.c: In function '__dn_count_labels': res_debug.c:1050:1: internal compiler error: RTL check: expected code 'reg', have 'const_int' in rhs_regno, at rtl.h:1934 1050 | } | ^ 0x8fb169 rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, int, char const*) ../.././gcc/gcc/rtl.cc:770 0x1399818 rhs_regno(rtx_def const*) ../.././gcc/gcc/rtl.h:1934 0x1399818 anticipatable_occurrence_p ../.././gcc/gcc/config/riscv/riscv-vsetvl.cc:348 So in this case avl should be obtained from dem. Another issue is caused by the following code: HOST_WIDE_INT diff = INTVAL (builder.elt (i)) - i; during RTL pass: expand ../../.././gcc/libgfortran/generated/matmul_c4.c: In function 'matmul_c4': ../../.././gcc/libgfortran/generated/matmul_c4.c:2906:39: internal compiler error: RTL check: expected code 'const_int', have 'const_poly_int' in expand_const_vector, at config/riscv/riscv-v.cc:1149 The builder.elt (i) can be either const_int or const_poly_int. PR target/111533 gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_const_vector): Fix bug. * config/riscv/riscv-vsetvl.cc (anticipatable_occurrence_p): Fix bug. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr111533-1.c: New test. * gcc.target/riscv/rvv/base/pr111533-2.c: New test. --- gcc/config/riscv/riscv-v.cc | 5 ++-- gcc/config/riscv/riscv-vsetvl.cc | 3 +- .../gcc.target/riscv/rvv/base/pr111533-1.c| 15 ++ .../gcc.target/riscv/rvv/base/pr111533-2.c| 29 +++ 4 files changed, 48 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-2.c diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 359fb2ced8b..26700cfc732 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1149,8 +1149,9 @@ expand_const_vector (rtx target, rtx src) for (unsigned int i = 0; i < v.npatterns (); ++i) { /* Calculate the diff between the target sequence and -vid sequence. */ - HOST_WIDE_INT diff = INTVAL (builder.elt (i)) - i; +vid sequence. The elt (i) can be either const_int or +const_poly_int. */ + poly_int64 diff = rtx_to_poly_int64 (builder.elt (i)) - i; v.quick_push (gen_int_mode (diff, v.inner_mode ())); } /* Step 2: Generate result = VID + diff. */ diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index 7af33e7ea6f..af8c31d873c 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -307,8 +307,7 @@ anticipatable_occurrence_p (const bb_info *bb, const vector_insn_info dem) if (dem.has_avl_reg ()) { /* rs1 (avl) are not modified in the basic block prior to the VSETVL. */ - rtx avl - = has_vl_op (insn->rtl ()) ? get_vl (insn->rtl ()) : dem.get_avl (); + rtx avl = dem.get_avl_or_vl_reg (); if (dem.dirty_p ()) { gcc_assert (!vsetvl_insn_p (insn->rtl ())); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-1.c new file mode 100644 index 000..aba26dfac89 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O2 -ffast-math -ftree-vectorize" } */ + +#include + +typedef _Complex float GFC_COMPLEX_4; + +void +test (GFC_COMPLEX_4 *a, GFC_COMPLEX_4 *b, GFC_COMPLEX_4 c, ptrdiff_t i, ptrdiff_t j) +{ + ptrdiff_t l; + for (l = 0; l <= i; ++l) +c += b[l] * a[j]; + b[j] = c; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-2.c new file mode 100644 index 000..a4d2011b74b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-2.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */ + +#include + +/* Return the number of DNS hierarchy levels in the name. */ +int +test (const char *name) { + int i, len, count; + + len = strlen(name); + for (i = 0, count = 0; i < len; i++) { + /* XXX need to check for \. or use named's nlabels(). */ + if (name[i] == '.') +