Re: [PATCH v2] RISC-V: T-HEAD: Add support for the XTheadInt ISA extension
On Tue, Jan 9, 2024 at 6:59 PM Jeff Law wrote: > > > > On 11/17/23 00:33, Jin Ma wrote: > > The XTheadInt ISA extension provides acceleration interruption > > instructions as defined in T-Head-specific: > > * th.ipush > > * th.ipop > > > > Ref: > > https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf > > > > gcc/ChangeLog: > > > > * config/riscv/riscv-protos.h (th_int_get_mask): New prototype. > > (th_int_get_save_adjustment): Likewise. > > (th_int_adjust_cfi_prologue): Likewise. > > * config/riscv/riscv.cc (TH_INT_INTERRUPT): New macro. > > (riscv_expand_prologue): Add the processing of XTheadInt. > > (riscv_expand_epilogue): Likewise. > > * config/riscv/riscv.md: New unspec. > > * config/riscv/thead.cc (BITSET_P): New macro. > > * config/riscv/thead.md (th_int_push): New pattern. > > (th_int_pop): New pattern. > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/riscv/xtheadint-push-pop.c: New test. > Thanks for the ping earlier today. I've looked at this patch repeatedly > over the last few weeks, but never enough to give it a full review. > > > > diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md > > index 2babfafb23c..4d6e16c0edc 100644 > > --- a/gcc/config/riscv/thead.md > > +++ b/gcc/config/riscv/thead.md > > > +(define_insn "th_int_pop" > > + [(unspec_volatile [(const_int 0)] UNSPECV_XTHEADINT_POP) > > + (clobber (reg:SI RETURN_ADDR_REGNUM)) > > + (clobber (reg:SI T0_REGNUM)) > > + (clobber (reg:SI T1_REGNUM)) > > + (clobber (reg:SI T2_REGNUM)) > > + (clobber (reg:SI A0_REGNUM)) > > + (clobber (reg:SI A1_REGNUM)) > > + (clobber (reg:SI A2_REGNUM)) > > + (clobber (reg:SI A3_REGNUM)) > > + (clobber (reg:SI A4_REGNUM)) > > + (clobber (reg:SI A5_REGNUM)) > > + (clobber (reg:SI A6_REGNUM)) > > + (clobber (reg:SI A7_REGNUM)) > > + (clobber (reg:SI T3_REGNUM)) > > + (clobber (reg:SI T4_REGNUM)) > > + (clobber (reg:SI T5_REGNUM)) > > + (clobber (reg:SI T6_REGNUM)) > > + (return)] > > + "TARGET_XTHEADINT && !TARGET_64BIT" > > + "th.ipop" > > + [(set_attr "type" "ret") > > + (set_attr "mode" "SI")]) > I probably would have gone with a load type since its the loads that are > most likely to interact existing code in the pipeline. But I doubt it > really matters in practice. > > > OK for the trunk. Thanks for your patience. I've retested this locally (no regressions), completed the ChangeLog in the commit message and committed. Thanks, Christoph
Re: [PATCH v2] RISC-V: T-HEAD: Add support for the XTheadInt ISA extension
On 11/17/23 00:33, Jin Ma wrote: The XTheadInt ISA extension provides acceleration interruption instructions as defined in T-Head-specific: * th.ipush * th.ipop Ref: https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf gcc/ChangeLog: * config/riscv/riscv-protos.h (th_int_get_mask): New prototype. (th_int_get_save_adjustment): Likewise. (th_int_adjust_cfi_prologue): Likewise. * config/riscv/riscv.cc (TH_INT_INTERRUPT): New macro. (riscv_expand_prologue): Add the processing of XTheadInt. (riscv_expand_epilogue): Likewise. * config/riscv/riscv.md: New unspec. * config/riscv/thead.cc (BITSET_P): New macro. * config/riscv/thead.md (th_int_push): New pattern. (th_int_pop): New pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadint-push-pop.c: New test. Thanks for the ping earlier today. I've looked at this patch repeatedly over the last few weeks, but never enough to give it a full review. diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md index 2babfafb23c..4d6e16c0edc 100644 --- a/gcc/config/riscv/thead.md +++ b/gcc/config/riscv/thead.md +(define_insn "th_int_pop" + [(unspec_volatile [(const_int 0)] UNSPECV_XTHEADINT_POP) + (clobber (reg:SI RETURN_ADDR_REGNUM)) + (clobber (reg:SI T0_REGNUM)) + (clobber (reg:SI T1_REGNUM)) + (clobber (reg:SI T2_REGNUM)) + (clobber (reg:SI A0_REGNUM)) + (clobber (reg:SI A1_REGNUM)) + (clobber (reg:SI A2_REGNUM)) + (clobber (reg:SI A3_REGNUM)) + (clobber (reg:SI A4_REGNUM)) + (clobber (reg:SI A5_REGNUM)) + (clobber (reg:SI A6_REGNUM)) + (clobber (reg:SI A7_REGNUM)) + (clobber (reg:SI T3_REGNUM)) + (clobber (reg:SI T4_REGNUM)) + (clobber (reg:SI T5_REGNUM)) + (clobber (reg:SI T6_REGNUM)) + (return)] + "TARGET_XTHEADINT && !TARGET_64BIT" + "th.ipop" + [(set_attr "type" "ret") + (set_attr "mode" "SI")]) I probably would have gone with a load type since its the loads that are most likely to interact existing code in the pipeline. But I doubt it really matters in practice. OK for the trunk. Thanks for your patience. jeff
Re:[PATCH v2] RISC-V: T-HEAD: Add support for the XTheadInt ISA extension
ping Ref: https://gcc.gnu.org/pipermail/gcc-patches/2023-November/636932.html
[PATCH v2] RISC-V: T-HEAD: Add support for the XTheadInt ISA extension
The XTheadInt ISA extension provides acceleration interruption
instructions as defined in T-Head-specific:
* th.ipush
* th.ipop
Ref:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf
gcc/ChangeLog:
* config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
(th_int_get_save_adjustment): Likewise.
(th_int_adjust_cfi_prologue): Likewise.
* config/riscv/riscv.cc (TH_INT_INTERRUPT): New macro.
(riscv_expand_prologue): Add the processing of XTheadInt.
(riscv_expand_epilogue): Likewise.
* config/riscv/riscv.md: New unspec.
* config/riscv/thead.cc (BITSET_P): New macro.
* config/riscv/thead.md (th_int_push): New pattern.
(th_int_pop): New pattern.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xtheadint-push-pop.c: New test.
---
gcc/config/riscv/riscv-protos.h | 3 +
gcc/config/riscv/riscv.cc | 61 ++-
gcc/config/riscv/riscv.h | 3 +
gcc/config/riscv/riscv.md | 4 +
gcc/config/riscv/thead.cc | 77 +++
gcc/config/riscv/thead.md | 67
.../gcc.target/riscv/xtheadint-push-pop.c | 36 +
7 files changed, 247 insertions(+), 4 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadint-push-pop.c
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 196b53f10f3..91d1e99f672 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -633,6 +633,9 @@ extern void th_mempair_prepare_save_restore_operands
(rtx[4], bool,
int, HOST_WIDE_INT,
int, HOST_WIDE_INT);
extern void th_mempair_save_restore_regs (rtx[4], bool, machine_mode);
+extern unsigned int th_int_get_mask (unsigned int);
+extern unsigned int th_int_get_save_adjustment (void);
+extern rtx th_int_adjust_cfi_prologue (unsigned int);
#ifdef RTX_CODE
extern const char*
th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE);
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index c2bd1c2ed29..6ff6f4789a4 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -94,15 +94,22 @@ along with GCC; see the file COPYING3. If not see
#define UNSPEC_ADDRESS_TYPE(X) \
((enum riscv_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
-/* True if bit BIT is set in VALUE. */
-#define BITSET_P(VALUE, BIT) (((VALUE) & (1ULL << (BIT))) != 0)
-
/* Extract the backup dynamic frm rtl. */
#define DYNAMIC_FRM_RTL(c) ((c)->machine->mode_sw_info.dynamic_frm)
/* True the mode switching has static frm, or false. */
#define STATIC_FRM_P(c) ((c)->machine->mode_sw_info.static_frm_p)
+/* True if we can use the instructions in the XTheadInt extension
+ to handle interrupts, or false. */
+#define TH_INT_INTERRUPT(c)\
+ (TARGET_XTHEADINT\
+ /* The XTheadInt extension only supports rv32. */ \
+ && !TARGET_64BIT\
+ && (c)->machine->interrupt_handler_p
\
+ /* The XTheadInt instructions can only be executed in M-mode. */ \
+ && (c)->machine->interrupt_mode == MACHINE_MODE)
+
/* Information about a function's frame layout. */
struct GTY(()) riscv_frame_info {
/* The size of the frame in bytes. */
@@ -6737,6 +6744,7 @@ riscv_expand_prologue (void)
unsigned fmask = frame->fmask;
int spimm, multi_push_additional, stack_adj;
rtx insn, dwarf = NULL_RTX;
+ unsigned th_int_mask = 0;
if (flag_stack_usage_info)
current_function_static_stack_size = constant_lower_bound (remaining_size);
@@ -6805,6 +6813,28 @@ riscv_expand_prologue (void)
REG_NOTES (insn) = dwarf;
}
+ th_int_mask = th_int_get_mask (frame->mask);
+ if (th_int_mask && TH_INT_INTERRUPT (cfun))
+{
+ frame->mask &= ~th_int_mask;
+
+ /* RISCV_PROLOGUE_TEMP may be used to handle some CSR for
+interrupts, such as fcsr. */
+ if ((TARGET_HARD_FLOAT && frame->fmask)
+ || (TARGET_ZFINX && frame->mask))
+ frame->mask |= (1 << RISCV_PROLOGUE_TEMP_REGNUM);
+
+ unsigned save_adjustment = th_int_get_save_adjustment ();
+ frame->gp_sp_offset -= save_adjustment;
+ remaining_size -= save_adjustment;
+
+ insn = emit_insn (gen_th_int_push ());
+
+ rtx dwarf = th_int_adjust_cfi_prologue (th_int_mask);
+ RTX_FRAME_RELATED_P (insn) = 1;
+ REG_NOTES (insn) = dwarf;
+}
+
/* Save the GP, FP registers. */
if ((frame->mask | frame->fmask) != 0)
{
@@ -7033,6 +7063,7 @@ riscv_expand_epilogue (int style)
= use_multi_pop ? frame->multi_push_adj_base +
