RE: [PATCH v2] arm: [MVE[ Add vqdmlashq intrinsics

2020-10-07 Thread Kyrylo Tkachov via Gcc-patches
Hi Christophe

> -Original Message-
> From: Gcc-patches  On Behalf Of
> Christophe Lyon via Gcc-patches
> Sent: 06 October 2020 16:59
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH v2] arm: [MVE[ Add vqdmlashq intrinsics
> 
> This patch adds:
> vqdmlashq_m_n_s16
> vqdmlashq_m_n_s32
> vqdmlashq_m_n_s8
> vqdmlashq_n_s16
> vqdmlashq_n_s32
> vqdmlashq_n_s8
> 
> v2: rebased after Srinath's reorganization patch
> 

Ok.
Thanks,
Kyrill

> 2020-10-05  Christophe Lyon  
> 
>   gcc/
>   PR target/96914
>   * config/arm/arm_mve.h (vqdmlashq, vqdmlashq_m): Define.
>   * config/arm/arm_mve_builtins.def (vqdmlashq_n_s)
>   (vqdmlashq_m_n_s,): New.
>   * config/arm/unspecs.md (VQDMLASHQ_N_S, VQDMLASHQ_M_N_S):
> New
>   unspecs.
>   * config/arm/iterators.md (VQDMLASHQ_N_S,
> VQDMLASHQ_M_N_S): New
>   attributes.
>   (VQDMLASHQ_N): New iterator.
>   * config/arm/mve.md (mve_vqdmlashq_n_, mve_vqdmlashq_m_n_s):
> New
>   patterns.
> 
>   gcc/tetsuite/
>   PR target/96914
>   * gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s16.c: New test.
>   * gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s32.c: New test.
>   * gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s8.c: New test.
>   * gcc.target/arm/mve/intrinsics/vqdmlashq_n_s16.c: New test.
>   * gcc.target/arm/mve/intrinsics/vqdmlashq_n_s32.c: New test.
>   * gcc.target/arm/mve/intrinsics/vqdmlashq_n_s8.c: New test.
> ---
>  gcc/config/arm/arm_mve.h   | 116 
> +
>  gcc/config/arm/arm_mve_builtins.def|   2 +
>  gcc/config/arm/iterators.md|   3 +
>  gcc/config/arm/mve.md  |  33 ++
>  gcc/config/arm/unspecs.md  |   2 +
>  .../arm/mve/intrinsics/vqdmlashq_m_n_s16.c |  23 
>  .../arm/mve/intrinsics/vqdmlashq_m_n_s32.c |  23 
>  .../arm/mve/intrinsics/vqdmlashq_m_n_s8.c  |  23 
>  .../arm/mve/intrinsics/vqdmlashq_n_s16.c   |  21 
>  .../arm/mve/intrinsics/vqdmlashq_n_s32.c   |  21 
>  .../gcc.target/arm/mve/intrinsics/vqdmlashq_n_s8.c |  21 
>  11 files changed, 288 insertions(+)
>  create mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s16.c
>  create mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s32.c
>  create mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s8.c
>  create mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s16.c
>  create mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s32.c
>  create mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s8.c
> 
> diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
> index d9bfb203..7626ad1 100644
> --- a/gcc/config/arm/arm_mve.h
> +++ b/gcc/config/arm/arm_mve.h
> @@ -141,6 +141,7 @@
>  #define vrev64q_m(__inactive, __a, __p) __arm_vrev64q_m(__inactive, __a,
> __p)
>  #define vqrdmlashq(__a, __b, __c) __arm_vqrdmlashq(__a, __b, __c)
>  #define vqrdmlahq(__a, __b, __c) __arm_vqrdmlahq(__a, __b, __c)
> +#define vqdmlashq(__a, __b, __c) __arm_vqdmlashq(__a, __b, __c)
>  #define vqdmlahq(__a, __b, __c) __arm_vqdmlahq(__a, __b, __c)
>  #define vmvnq_m(__inactive, __a, __p) __arm_vmvnq_m(__inactive, __a,
> __p)
>  #define vmlasq(__a, __b, __c) __arm_vmlasq(__a, __b, __c)
> @@ -260,6 +261,7 @@
>  #define vorrq_m(__inactive, __a, __b, __p) __arm_vorrq_m(__inactive, __a,
> __b, __p)
>  #define vqaddq_m(__inactive, __a, __b, __p) __arm_vqaddq_m(__inactive,
> __a, __b, __p)
>  #define vqdmladhq_m(__inactive, __a, __b, __p)
> __arm_vqdmladhq_m(__inactive, __a, __b, __p)
> +#define vqdmlashq_m(__a, __b, __c, __p) __arm_vqdmlashq_m(__a, __b,
> __c, __p)
>  #define vqdmladhxq_m(__inactive, __a, __b, __p)
> __arm_vqdmladhxq_m(__inactive, __a, __b, __p)
>  #define vqdmlahq_m(__a, __b, __c, __p) __arm_vqdmlahq_m(__a, __b, __c,
> __p)
>  #define vqdmlsdhq_m(__inactive, __a, __b, __p)
> __arm_vqdmlsdhq_m(__inactive, __a, __b, __p)
> @@ -1307,6 +1309,7 @@
>  #define vqdmlsdhxq_s8(__inactive, __a, __b)
> __arm_vqdmlsdhxq_s8(__inactive, __a, __b)
>  #define vqdmlsdhq_s8(__inactive, __a, __b)
> __arm_vqdmlsdhq_s8(__inactive, __a, __b)
>  #define vqdmlahq_n_s8(__a, __b, __c) __arm_vqdmlahq_n_s8(__a, __b, __c)
> +#define vqdmlashq_n_s8(__a, __b, __c) __arm_vqdmlashq_n_s8(__a, __b,
> __c)
>  #define vqdmladhxq_s8(__inactive, __a, __b)
> __arm_vqdmladhxq_s8(__inactive, __a, __b)
>  #define vqdmladhq_s8(__inactive, __a, __b)
> __arm_vqdmladhq_s8(__inactive, __a, __b)
>  #define vmlsdavaxq_s8(__a, __b, __c

[PATCH v2] arm: [MVE[ Add vqdmlashq intrinsics

2020-10-06 Thread Christophe Lyon via Gcc-patches
This patch adds:
vqdmlashq_m_n_s16
vqdmlashq_m_n_s32
vqdmlashq_m_n_s8
vqdmlashq_n_s16
vqdmlashq_n_s32
vqdmlashq_n_s8

v2: rebased after Srinath's reorganization patch

2020-10-05  Christophe Lyon  

gcc/
PR target/96914
* config/arm/arm_mve.h (vqdmlashq, vqdmlashq_m): Define.
* config/arm/arm_mve_builtins.def (vqdmlashq_n_s)
(vqdmlashq_m_n_s,): New.
* config/arm/unspecs.md (VQDMLASHQ_N_S, VQDMLASHQ_M_N_S): New
unspecs.
* config/arm/iterators.md (VQDMLASHQ_N_S, VQDMLASHQ_M_N_S): New
attributes.
(VQDMLASHQ_N): New iterator.
* config/arm/mve.md (mve_vqdmlashq_n_, mve_vqdmlashq_m_n_s): New
patterns.

gcc/tetsuite/
PR target/96914
* gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s16.c: New test.
* gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s32.c: New test.
* gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s8.c: New test.
* gcc.target/arm/mve/intrinsics/vqdmlashq_n_s16.c: New test.
* gcc.target/arm/mve/intrinsics/vqdmlashq_n_s32.c: New test.
* gcc.target/arm/mve/intrinsics/vqdmlashq_n_s8.c: New test.
---
 gcc/config/arm/arm_mve.h   | 116 +
 gcc/config/arm/arm_mve_builtins.def|   2 +
 gcc/config/arm/iterators.md|   3 +
 gcc/config/arm/mve.md  |  33 ++
 gcc/config/arm/unspecs.md  |   2 +
 .../arm/mve/intrinsics/vqdmlashq_m_n_s16.c |  23 
 .../arm/mve/intrinsics/vqdmlashq_m_n_s32.c |  23 
 .../arm/mve/intrinsics/vqdmlashq_m_n_s8.c  |  23 
 .../arm/mve/intrinsics/vqdmlashq_n_s16.c   |  21 
 .../arm/mve/intrinsics/vqdmlashq_n_s32.c   |  21 
 .../gcc.target/arm/mve/intrinsics/vqdmlashq_n_s8.c |  21 
 11 files changed, 288 insertions(+)
 create mode 100644 
gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s16.c
 create mode 100644 
gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s32.c
 create mode 100644 
gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s8.c
 create mode 100644 
gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s16.c
 create mode 100644 
gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s32.c
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s8.c

diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index d9bfb203..7626ad1 100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -141,6 +141,7 @@
 #define vrev64q_m(__inactive, __a, __p) __arm_vrev64q_m(__inactive, __a, __p)
 #define vqrdmlashq(__a, __b, __c) __arm_vqrdmlashq(__a, __b, __c)
 #define vqrdmlahq(__a, __b, __c) __arm_vqrdmlahq(__a, __b, __c)
+#define vqdmlashq(__a, __b, __c) __arm_vqdmlashq(__a, __b, __c)
 #define vqdmlahq(__a, __b, __c) __arm_vqdmlahq(__a, __b, __c)
 #define vmvnq_m(__inactive, __a, __p) __arm_vmvnq_m(__inactive, __a, __p)
 #define vmlasq(__a, __b, __c) __arm_vmlasq(__a, __b, __c)
@@ -260,6 +261,7 @@
 #define vorrq_m(__inactive, __a, __b, __p) __arm_vorrq_m(__inactive, __a, __b, 
__p)
 #define vqaddq_m(__inactive, __a, __b, __p) __arm_vqaddq_m(__inactive, __a, 
__b, __p)
 #define vqdmladhq_m(__inactive, __a, __b, __p) __arm_vqdmladhq_m(__inactive, 
__a, __b, __p)
+#define vqdmlashq_m(__a, __b, __c, __p) __arm_vqdmlashq_m(__a, __b, __c, __p)
 #define vqdmladhxq_m(__inactive, __a, __b, __p) __arm_vqdmladhxq_m(__inactive, 
__a, __b, __p)
 #define vqdmlahq_m(__a, __b, __c, __p) __arm_vqdmlahq_m(__a, __b, __c, __p)
 #define vqdmlsdhq_m(__inactive, __a, __b, __p) __arm_vqdmlsdhq_m(__inactive, 
__a, __b, __p)
@@ -1307,6 +1309,7 @@
 #define vqdmlsdhxq_s8(__inactive, __a, __b) __arm_vqdmlsdhxq_s8(__inactive, 
__a, __b)
 #define vqdmlsdhq_s8(__inactive, __a, __b) __arm_vqdmlsdhq_s8(__inactive, __a, 
__b)
 #define vqdmlahq_n_s8(__a, __b, __c) __arm_vqdmlahq_n_s8(__a, __b, __c)
+#define vqdmlashq_n_s8(__a, __b, __c) __arm_vqdmlashq_n_s8(__a, __b, __c)
 #define vqdmladhxq_s8(__inactive, __a, __b) __arm_vqdmladhxq_s8(__inactive, 
__a, __b)
 #define vqdmladhq_s8(__inactive, __a, __b) __arm_vqdmladhq_s8(__inactive, __a, 
__b)
 #define vmlsdavaxq_s8(__a, __b, __c) __arm_vmlsdavaxq_s8(__a, __b, __c)
@@ -1391,6 +1394,7 @@
 #define vqrdmladhq_s16(__inactive, __a, __b) __arm_vqrdmladhq_s16(__inactive, 
__a, __b)
 #define vqdmlsdhxq_s16(__inactive, __a, __b) __arm_vqdmlsdhxq_s16(__inactive, 
__a, __b)
 #define vqdmlsdhq_s16(__inactive, __a, __b) __arm_vqdmlsdhq_s16(__inactive, 
__a, __b)
+#define vqdmlashq_n_s16(__a, __b, __c) __arm_vqdmlashq_n_s16(__a, __b, __c)
 #define vqdmlahq_n_s16(__a, __b, __c) __arm_vqdmlahq_n_s16(__a, __b, __c)
 #define vqdmladhxq_s16(__inactive, __a, __b) __arm_vqdmladhxq_s16(__inactive, 
__a, __b)
 #define vqdmladhq_s16(__inactive, __a, __b) __arm_vqdmladhq_s16(__inactive, 
__a, __b)
@@ -1476,6 +1480,7 @@
 #define vqrdmladhq_s32(__inactive, __a, __b)