In one place we open-code a special case of this pattern into the more specific sub<GPI>3_compare1_imm, and miss this special case in other places. Centralize that special case into an expander.
* config/aarch64/aarch64.md (*sub<GPI>3_compare1): Rename from sub<GPI>3_compare1. (sub<GPI>3_compare1): New expander. * config/aarch64/aarch64.c (aarch64_expand_subvti): Remove call to gen_subdi3_compare1_imm. --- gcc/config/aarch64/aarch64.c | 11 ++--------- gcc/config/aarch64/aarch64.md | 22 +++++++++++++++++++++- 2 files changed, 23 insertions(+), 10 deletions(-) diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index c90de65de12..7a13a8e8ec4 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -20333,16 +20333,9 @@ aarch64_expand_subvti (rtx op0, rtx low_dest, rtx low_in1, } else { - if (aarch64_plus_immediate (low_in2, DImode)) - emit_insn (gen_subdi3_compare1_imm (low_dest, low_in1, low_in2, - GEN_INT (-INTVAL (low_in2)))); - else - { - low_in2 = force_reg (DImode, low_in2); - emit_insn (gen_subdi3_compare1 (low_dest, low_in1, low_in2)); - } - high_in2 = force_reg (DImode, high_in2); + emit_insn (gen_subdi3_compare1 (low_dest, low_in1, low_in2)); + high_in2 = force_reg (DImode, high_in2); if (unsigned_p) emit_insn (gen_usubdi3_carryinC (high_dest, high_in1, high_in2)); else diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index b242f2b1c73..d6389cc8148 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3120,7 +3120,7 @@ [(set_attr "type" "alus_imm")] ) -(define_insn "sub<mode>3_compare1" +(define_insn "*sub<mode>3_compare1" [(set (reg:CC CC_REGNUM) (compare:CC (match_operand:GPI 1 "aarch64_reg_or_zero" "rkZ") @@ -3132,6 +3132,26 @@ [(set_attr "type" "alus_sreg")] ) +(define_expand "sub<mode>3_compare1" + [(parallel + [(set (reg:CC CC_REGNUM) + (compare:CC + (match_operand:GPI 1 "aarch64_reg_or_zero") + (match_operand:GPI 2 "aarch64_reg_or_imm"))) + (set (match_operand:GPI 0 "register_operand") + (minus:GPI (match_dup 1) (match_dup 2)))])] + "" +{ + if (aarch64_plus_immediate (operands[2], <MODE>mode)) + { + emit_insn (gen_sub<mode>3_compare1_imm + (operands[0], operands[1], operands[2], + GEN_INT (-INTVAL (operands[2])))); + DONE; + } + operands[2] = force_reg (<MODE>mode, operands[2]); +}) + (define_peephole2 [(set (match_operand:GPI 0 "aarch64_general_reg") (minus:GPI (match_operand:GPI 1 "aarch64_reg_or_zero") -- 2.20.1